H7 ADC minimum Sampling Time for slow channels?

[Asantos]

What is the minimum Sampling Time for ADC slow channels in the STM32H7?

Ari

[Khouloud GARSI]

Hello @Community member​ ,

The minimum sampling time is 1.5 ADC clock cycles.

Please refer to table "ADC characteristics" in the datasheet for further details.

Khouloud.

[Asantos]

Khouloud,

1.5 ADC clock cycles for what ADC clock frequency?

According to the datasheet, 1.5 clock cycles is the minimum sampling time for the fast channels when the ADC clock is 36MHZ. So the minimum sampling time is 1.5/36MHZ = 41.7nS.

What I need to now is the minimum sampling time in nS, or the minimum cycles number, for the slow channels when the ADC clock is 36MHZ.

The datasheet only has a table showing the conversion times for the slow channels for an ADC clock of 10 MHZ. If the ADC clock were 36MHZ in the table, it would be possible to deduce the minimum sample time.

Ari.

[Khouloud GARSI]

Hi Ari,

Sampling rate for Fast channels, BOOST = 1, fADC = 36 MHz (16-bit resolution) is 3.6 MSPS.

Sampling rate for Slow channels, BOOST = 0, fADC = 10 MHz, (16-bit resolution)is 1 MSPS.

the sampling time for slow channels when fADC = 10 MHz is:

1/10MHz*1.5 = 150 ns.

Even if you're using fADC = 36 MHz, the sampling rate is always limited to 150ns.

So, the sampling time for slow channels when fADC = 36 MHz is:

1/36MHz*X < 150 ns -> X<5.4 ADC clock cycles

Thus, the minimum sampling time you can use is 8.5 ADC clock cycles. 

Khouloud.

[Asantos]

Thanks Khouloud.

So the minimum sampling time for the H7 ADC's is 41.7nS for fast channels and 150nS for slow channels.

It is interesting to note that the slow channel of the H7 is much slower than that of the F3 and the L4.

62.5 nS and 81.25 nS respectively.

Ari.