Grouping of peripherals in CubeF0

[waclawek.jan]

Posted on December 15, 2016 at 16:50

What is the purpose of GRP{x} in LL_{BUS}_GRP{x}_EnableClock() in CubeF0?

Where is it documented?

Thanks,

JW

[Imen.D]

Posted on December 21, 2016 at 18:41

Dear

Waclawek.Jan

‌,

You can reviewthe

http://www.st.com/content/ccc/resource/technical/document/user_manual/2f/77/25/0f/5c/38/48/80/DM00122pdf/files/DM00122pdf/jcr:content/translations/en.DM00122pdf

Description of STM32F0xx HAL and Low-layer drivers

Best Regards

Imen

[waclawek.jan]

Posted on December 21, 2016 at 19:32

Imen,

Thanks for the hint.

Threw on me a 1300-page (most of it doxygen-autovomited) pdf to keep me busy, huh? ;)

So on page 67 I found:

'x' corresponds to the group index and refers to the index of the modified register on a given bus.

Ah....a bit of reading of RM0091... I now understand. There is a single APB bus in the 'F0x, but there are quite a lot of peripherals on it so that the enable/reset RCC registers have been split (there are 31 active bits in them, incidentally, which would fit into a single 32-bit register; the reserved spaces between bits hint that there is an upward expansion plan). So the x in GRPx is the same x as in the RCC_APBxENR (and 'RSTR).

If you ask me, this is again a poor choice of register naming, as it is inconsistent. The same x in RCC_APBxENR in other STM32 families indicates the number of APB bus; when the bits for one bus are split this is indicated as y in RCC_APBxENRy - see e.g. RM0351.

JW