GPIO speed

[marcogrossi89]

Posted on October 06, 2015 at 17:31

I am working on a STM32 NUCLEO 152RE.

When initializing a I/O pin of a digital port, one of the options is to set its speed. The available options for L152 are:

GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */

  GPIO_Speed_2MHz   = 0x01, /*!< Low Speed */

  GPIO_Speed_10MHz  = 0x02, /*!< Medium Speed */

  GPIO_Speed_40MHz  = 0x03  /*!< High Speed */

However the GPIO frequency cannot be higher than HCLK.

If, for example, I set the SystemClock to 12MHz (HSI with PLLMul 3 and PLLDiv 4) with no AHB prescaler, HCLK is 12MHz.

Then, what happens if I set GPIO_Speed_40MHz for a digital I/O? Is the pin speed scaled down to the highest frequency possible (12MHz) or what else?

Thanks.

[waclawek.jan]

Posted on October 06, 2015 at 17:53

This sets output driver strength (or slew rate if you wish) and has nothing to do with clocks at all.

Look at the datasheet's GPIO section to see the effect of different values.

JW

[Tesla DeLorean]

Posted on October 06, 2015 at 18:56

I prefer slew, but it's how aggressively the edges are driven, and there are occasions where setting it below what you're actually outputting are preferable, especially where the signal go into input that presents a low loading, uses short traces or doesn't like hard under/over-shoot and ringing that can occur otherwise. The STM32F429 SDRAM being a specific example where 100 MHz signals select a 50 MHz setting.

For a USART 1MHz should be more than adequate for 99.999% of application. The same goes for I2C. For SPI and SDIO 25 MHz might be more appropriate, but again depending on how you're actually using the interface.

The idea is to pick a number that's most appropriate for a specific interface, as it reduces the noise and under/over-shoot on the pin, and reduces the current surges at CMOS switching frequencies.