fsmc configuration for multiplexed memory

[torturecell]

Posted on June 08, 2012 at 23:56

Hello all,

I am using stm32f217 on my target board. it has a mutiplexed 8MB psram. My problem is my one 16bit write changes the value written by previous 16bit write.

write_ram16(0,0xaaaa)-->16 bit write at offset 0, base add 0x60000000

write_ram16(2,0xf000)

read_ram16(2) --> returns 0xf000

read_ram16(0) -->returns 1

my fsmc config is

FSMC_Bank1->BCR1 = (FSMC_BCR_MBKEN | //bank enable

                                         FSMC_BCR_MTYP_PSRAM | //memory is psram

                                         FSMC_BCR_MWID_16BITS |//16bit wide

                                         FSMC_BCR_WREN |  //write enable

                                         FSMC_BCR_MUXEN); //mux enable

FSMC_Bank1->BTR1 =  0x00010401; //DataSetupTime = 4, BusTurnAroundDuration = 1, add setup=1

[alok472]

Posted on June 09, 2012 at 08:50

would be good if you can provide the Schematics for review.

Better to use the Fw library example on FSMC

[torturecell]

Posted on June 09, 2012 at 13:14

Hello alokm,

i think in the FW library example, the ram is connected in non multiplexed way. is it right or is there any example where ram is connected in multiplexed way also?

attached are the gpio and sram schematics

________________

Attachments :

gpio.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtUW&d=%2Fa%2F0X0000000aQl%2FPi3cW8s7QgKKBllhaVpZUrVfUeiYrLOwsnwWEvSgr4o&asPdf=false

sram.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtUb&d=%2Fa%2F0X0000000aQm%2F8Msf1nrrcyE2BDIYP.KZj1GDq4RrJKFydn3T76iznK8&asPdf=false

[balmukund66]

Posted on June 11, 2012 at 15:41

Hi,

according to you , You are reading the same data as you have written in the last.

can you explain  the following function write_ram16() & read_ram16().There may be error in address handling .

Regards

Balmukund prasad

[alok472]

Posted on June 13, 2012 at 03:16

from the schematics, nothing seems wrong. Can you change the FSMC settings to allow more time for RAM to setup the data on data bus ? maybe it's timing problem.

i am not aware of any schm of mux-ed ram. there do exist an AN on FSMC, not sure if it talks about the mux mode of fsmc

[torturecell]

Posted on June 13, 2012 at 21:33

Hello Prasad,

read and write functions are quite straightforward. below is the implementation.

uint16_t read_ram16(uint32_t offset)

{

    volatile uint16_t * t=(0x60000000+offset);

    return *t;

}

void write_ram16(uint32_t offset,uint16_t data)

{

    volatile uint16_t * t=(0x60000000+offset);

    *t = data;

}

[zaurozavr]

Posted on July 01, 2012 at 20:15

You are wrong in schematics. NL line should be inverted.  Otherwise  (as in you case) you'll see  a latched data instead of RAM content (and RAM content differs from that you may expect).