FSMC Byte Lane Signals Not Pulsing as Expected with SRAM

[design5]

Posted on August 10, 2009 at 16:51

FSMC Byte Lane Signals Not Pulsing as Expected with SRAM

[design5]

Posted on May 17, 2011 at 13:20

Fellow Programmers:

It gets pretty bad when you have to reply to your own Posting to tell yourself where you goofed up.

The problem is solved.

Garry's Rule #6: ''When a signal does not appear to be working, as it should, make sure you enabled the GPIO pin so the signal can get out of the chip.''

In this case, dummy Garry forgot to enable the Byte Lane pins for the FSMC Controller.

Happy programming.

Garry.

[design5]

Posted on May 17, 2011 at 13:20

Hi Tech Support:

I have a 16-bit wide SRAM connected to FSMC. I have configured the memory width as 16b. I am using Mode_1 (viz: Mode_A with ExpMode = 0). I am testing byte access to see the Byte Lane operation, but there is no Byte Lane activity.

I am testing my FSMC access to my external SRAM (via NE2) with the following test code:

u8 i;

u8* p;

while(1)

{

// put some test data in external RAM

p = (u8 *)0x64000000;

for(i = 1; i < 5; ++i)

{

*p = i;

++p;

}

}

I expect to see the Byte Lane signals pulsing for the high and low byte writes, but, both NBL1 and NBL0 remain low all the time. I am connecting the oscilloscope directly onto the RAM pins. The NE2 line is working, and the A0 and A1 lines are only following word access, only changing every two bytes, which appears to be correct (two NE2 pulses with A0 low, followed by two NE2 pulses with A0 high).

Any ideas what I am doing wrong?

Thanks,

Garry.