FSMC Base Address Calculation Problems

[reubeninbminor3]

Posted on July 13, 2014 at 18:39

Hello All,

I have designed a board based on STM32F103VGT(100 pin, 1MB flash memory) which utilizes the FSMC to drive SSD1963 in 8 bit mode.

I have connected FSMC_A17 to the SSD1963 RS, and FSMC_NE1 to SSD1963 CS.

After reading up a bit, I calculated the FSMC address as:

&sharpdefine LCD_BASE           ((uint32_t)(0x60000000 | ((0UL << 27) | (0UL << 26))) | (1UL << 17))

Is this the  calculation correct ?

I have connected a Logic Analyzer, but I do not see any activity on RS or Data lines.

The CS line works as expected.

My FSMC init code is :

FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;

  FSMC_NORSRAMTimingInitTypeDef  p;

  /*-- FSMC Configuration -----------------------------------------------------*/

  /*----------------------- SRAM Bank 1 ---------------------------------------*/

  /* FSMC_Bank1_NORSRAM1 configuration */

  p.FSMC_AddressSetupTime = 1;

  p.FSMC_AddressHoldTime = 0;

  p.FSMC_DataSetupTime = 2;

  p.FSMC_BusTurnAroundDuration = 0;

  p.FSMC_CLKDivision = 0;

  p.FSMC_DataLatency = 0;

  p.FSMC_AccessMode = FSMC_AccessMode_A;

  /* Color LCD configuration

     LCD configured as follow:

        - Data/Address MUX = Disable

        - Memory Type = SRAM

        - Data Width = 8bit

        - Write Operation = Enable

        - Extended Mode = Enable

        - Asynchronous Wait = Disable */

  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;

  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;

  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;

  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;

  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;

  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;

  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;

  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;

  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;

  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;

  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  

  /* BANK 1 (of NOR/SRAM Bank 1~4) is enabled */

  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);

#ssd1963-fsmc-lcd #base #calculate

[Tesla DeLorean]

Posted on July 13, 2014 at 20:00

The address looks Ok, perhaps you should review the pin configuration, and examples in STM3210E-EVAL, etc

[reubeninbminor3]

Posted on July 14, 2014 at 15:21

Hi Clive, thanks for your reply.

My pin configuration is :

GPIO_InitTypeDef GPIO_InitStructure;

    /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */

    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);

    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |

                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |

                         RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA, ENABLE);

    /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),

     PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull

    Added PD.12 for A17=RS

    Added PD.07 for CS

    */

    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |

                                GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |

                                GPIO_Pin_15 | GPIO_Pin_12 | GPIO_Pin_7;

    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

    GPIO_Init(GPIOD, &GPIO_InitStructure);

    /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),

     PE.14(D11), PE.15(D12) as alternate function push pull */

    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |

                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |

                                GPIO_Pin_15;

    GPIO_Init(GPIOE, &GPIO_InitStructure);

    // added PD.02 below for LCD Reset

    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;

    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;

    GPIO_Init(GPIOD, &GPIO_InitStructure);

I'm using Keil, and in debug, I can see the pins set appropriately in ''Peripherals->GPIO''

Can you find any mistake I might be making ?

As for the example, I've just grabbed the same, and changed the pins above to match my board.

Can it be that the STM32F103VGT doesn't support A17, or maybe Bank1, sub bank-1 ?

I've double, triple checked the datasheet, but maybe I'm missing something ?

Thanks again.