fsmc and nand flash

[jbl_raw]

Posted on January 11, 2013 at 02:12

1-i'm confused in datasheet i see 4x64mb per bank . it's means maximum of  each nand flash is 64mbyte .

2- in the AN2790 Application note  about lcd with fsmc.

read from NAND Flash 11 fps

read fron sd card   12fps

why the sd card faster than nand flash sd card is serial and. nand flash  is parallel

and read time is 25ns per byte it means 40mbyte per second read speed.

[Tesla DeLorean]

Posted on January 11, 2013 at 03:17

NAND memories access as block devices, they don't provide linear access like NOR. You access them through a window, and can therefore provide huge amounts of storage in a much smaller address space.

Accessing the blocks within a NAND is relatively slow, you must request that it retrieves data, wait for it to be ready, and then pull it out. Pulling it out relates to the bandwidth of your bus. You should review your NAND docs/specs and understand the block/page read/write times.

SD cards place a NAND controller in front of the NAND memories, this can provide for additional buffering, caching, and prefetch, along with error correction. Aspects of which you'll have to get painfully involved in by talking to the NAND memories directly.

[jbl_raw]

Posted on January 11, 2013 at 15:08

thank you :)

what about this question

1-i'm confused in datasheet i see 4x64mb per bank . it's means maximum of  each nand flash is 64mbyte ? .

[frankmeyer9]

Posted on January 11, 2013 at 15:54

what about this question

 

1-i'm confused in datasheet i see 4x64mb per bank . it's means maximum of  each nand flash is 64mbyte ? .

 

Count the number of available address pins in the FSMC interface, and you know why.

[Tesla DeLorean]

Posted on January 11, 2013 at 15:57

64 MB x 4 = 256 MB (0x10000000)

This is the size of the address decode bank within the STM32, this has NO bearing on the capacity of the attached NAND if you understand how the memory is accessed. The NAND is NOT a byte addressable memory.

[jbl_raw]

Posted on January 11, 2013 at 16:32

thank all for fast reply  :)

i will buy 512mbyte very fast nand flash. and execute programm code from it .

[Tesla DeLorean]

Posted on January 11, 2013 at 17:20

i will buy 512mbyte very fast nand flash. and execute programm code from it .

Again, it's not byte addressable, you can't execute code from it. Think of it like a hard drive, or other block device. If you want code execution use SRAM or NOR.

[jbl_raw]

Posted on January 15, 2013 at 20:50

i see some data sheet about nor flash and sram. but all very slow  .compared with internal flash and sram . if i use two sram and two nor flash it will increase speed and capacity. or will increase capacity only

[Tesla DeLorean]

Posted on January 15, 2013 at 22:12

Well you have a couple of issues, the Cortex-M3 is designed to used tightly coupled memories for rapid execution, it does not have a cache mechanism to defray the slow speed of external memories. The ART cache which masks the intrinsic slowness of the internal flash is tailored to that specific architecture, and represent a critical path for prefetch accesses. External memory accesses on ST parts have historically been slow, driving the bus also takes a lot of power as it has to escape the core, and boost the current/voltage. ST parts (STR9, STR7, STM32) do not support SDRAM, so you are pushed into more expensive and lower capacity parts when adding external memory.

Consider a 2MB FLASH version of the STM32F4 family.

http://www.st.com/internet/com/press_release/p3357.jsp

If that still isn't enough, start considering other architectures. Perhaps an ARM9 core, with caching and SDRAM support. Or an A-series part targeting phones/tablets.

[jbl_raw]

Posted on January 20, 2013 at 19:37

thank you for your help and full support :) .

when i add an external nor flash. can i make some function execute from external nor memory . and some function execute from internal flash memory.

[Tesla DeLorean]

Posted on January 21, 2013 at 01:00

You'd need to describe the regions of memory in your GUI, scatter file or linker script. You'd define sections within these regions, and then direct the compiler to place specific functions or objects within those sections.

To program the code into these memories you'd need to tell your debug tools about how to write into the NOR via an applet or macro. You could also do it yourself (provide routines to download), or use something like J-Flash