Frequency Meansure

[felipe]

Posted on May 15, 2014 at 17:06

Hi,  I am using uvision4 with stm32f1xx to meansure frequency counting the time of the falling edge pulse. I need a high precision to meansure frequency from 0Hz to 240Hz. The first thing that I do was to set the prescaler to mensure 240Hz. That is ok, the problem is that I cant get when the timer count overflow to mensure frequency from 61 to 0. The program enter in theTIM_IT_Update all the time, what am I doing wrong?     void RCC_Configuration(void){

/* TIM2 clock enable */

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); TIM_TimeBaseStructure.TIM_Period = 65535; //20 mS

TIM_TimeBaseStructure.TIM_Prescaler = Prescaler_Pickup - 1; //1 uS 1 MHz

TIM_TimeBaseStructure.TIM_ClockDivision = 0;

TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;

TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

}   void TIM2_IRQHandler (void) {

if(TIM_GetITStatus(TIM2, TIM_IT_CC1) == SET){

/* Clear TIM3 Capture compare interrupt pending bit */

TIM_ClearITPendingBit(TIM2, TIM_IT_CC1);

if(CaptureNumber == 0){

/* Get the Input Capture value */

IC3ReadValue1 = TIM_GetCapture1(TIM2);

CaptureNumber = 1;

estourou_timer = 0;

}

else if(CaptureNumber == 1){

/* Get the Input Capture value */

IC3ReadValue2 = TIM_GetCapture1(TIM2);

/* Capture computation */

if (IC3ReadValue2 > IC3ReadValue1){

Capture = (estourou_timer * 65535) + (IC3ReadValue2 - IC3ReadValue1);

}

else{

Capture = (estourou_timer * 65535) + ((0xFFFF - IC3ReadValue1) + IC3ReadValue2);

}

/* Frequency computation */

Pickup_1_FLOAT = (float) (72000000/Prescaler_Pickup) / Capture;

if(Pickup_1_FLOAT < Menor_Med) Menor_Med = Pickup_1_FLOAT;

CaptureNumber = 0;

}

}

if((TIM_GetITStatus(TIM2, TIM_IT_Update) == SET )){ //overflow

TIM_ClearITPendingBit(TIM2, TIM_FLAG_Update);

estourou_timer++;

}

}   void TIM2_Configuration(){

TIM_ICInitStructure.TIM_Channel = TIM_Channel_1;

TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;

TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;

TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;

TIM_ICInitStructure.TIM_ICFilter = 0x0;

TIM_ICInit(TIM2, &TIM_ICInitStructure); /* TIM enable counter */

TIM_Cmd(TIM2, ENABLE);

/* Enable the CC1 Interrupt Request */

TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_Update, ENABLE);

TIM_ICInit(TIM2, &TIM_ICInitStructure); /* TIM enable counter */

TIM_Cmd(TIM2, ENABLE);    /* Enable the TIM3 global Interrupt */  NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQChannel;  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;  NVIC_Init(&NVIC_InitStructure);      }      

[felipe]

Posted on May 20, 2014 at 14:16

Thanks again for the reply.

As I said in the other post, the problem is not that I'm not getting the overflow.

The processor keep entering in the if braces in frequencies that no overflow occur.

Obviously I'm using it in a ISR interrupt.

I tried to enable the overflow/re-load IRQ using TIMx_CR1 register UDIS bit but still the processor enter in the if braces with no overflow.

[chen]

Posted on May 20, 2014 at 14:59

''I tried to enable the overflow/re-load IRQ using TIMx_CR1 register UDIS bit but still the processor enter in the if braces with no overflow.''

There are a number of reason why this may be.

One of them is that reading the status register will clear certain states. The overflow is one of them.

[felipe]

Posted on May 20, 2014 at 15:12

If I ready the SR register I will reset the overflow?

Just reading it like that:

''if ((TIM2->SR & 0x0001) != 0)

'' Even when the Update interrupt flag isnt Updated? Can I change this?

[chen]

Posted on May 20, 2014 at 15:43

''If I ready the SR register I will reset the overflow?''

That is what I implied but re-reading the reference manual - not sure now.

I think you will have to try an experimental piece of code to prove it one way or anoher.

Another thing - I do not think I see any code which sets the overflow value (the ARR register).

I think ARR = 0 is invalid and will never generate an IRQ.

[sdim]

Posted on May 21, 2014 at 12:12

You can try a different approach.

Use a master timer and a slave timer. Select the update event of the master timer as trigger output . The master timer can be used as a prescaler for the slave timer.

( Application note AN4013 , timer overview)

[felipe]

Posted on May 21, 2014 at 14:13

Sung,

 

I have tested and reading the SR register isnt reseting the overflow.

I still think that I dont configure the TIM_IT_Update to only happen when a overflow occur. Because the code still enter in the braces in high frequencies, where no overflow ocurred.

I tried to put 65535 in the ARR register, enable ARPE bit 7 of TIMx_CR1 but not lucky.

Dimopoulos,

Thanks for the reply.

I've seen this application note.

 But to do it I will have to change my hardware.

Doing the measure the way I am trying, I think that I will get a 0Hz rapid and also verify if a cable of metering is broken in a faster way.

 

[sdim]

Posted on May 21, 2014 at 16:44

The timers are linked internally, there is no need to modify the hardware.

[felipe]

Posted on May 21, 2014 at 16:56

Dimopoulos,

Are you sure?

I was seeing this Application note AN2592 Figure 2.

So I tought that the input sinal have to enter in 2 pins.

[felipe]

Posted on May 23, 2014 at 14:30

I realy dont get it.

The overflow of the master timer is used to clock slave counter.

So acordding to AN2592 the to timers are configured as input capture.

What the slave timer capture?

[sdim]

Posted on May 24, 2014 at 08:44

The timer synchronization is described on 

http://www.st.com/web/en/resource/technical/document/application_note/DM00042534.pdf

, not AN2592.

AN4013 Application Note: STM32F0, STM32F1, STM32F2, STM32F4, STM32L1 series,STM32F30xC/Bx, STM32F358xC, STM32F37x, timer overview

''3.1 Timer system link

STM32 timers are linked together internally for timer synchronization or chaining. Each timer has several internal trigger inputs and outputs. These signals allow the timer to be connected with other timers.''