FMC Issue with Allignment

[PBU]

I am trying to read/ write data into FMC SDRAM (16 bit) in Bank 1. While writing the data hard fault occurred. What is the reason for that hard fault, is there any problem with data alignment, If yes what is the solution for it ?

[Tesla DeLorean]

Hard Faults will occur if you step outside of the bounds of physical memory. For alignment, the Cortex-Mx parts will fault on unaligned reads/writes on instructions like LDRD/STRD, but most other situations where you span two 32-bit word boundaries are managed by the CPU or buses.

Inspect the faulting instructions, and the registers, to understand what is being objected too.