FMC behaviour if read before a previous write cycle has completed

[Konrad1]

I connecting an FPGA slave to an STM32F7 FMC 'sram' bus. For this particular project, I need to access the bus both inside and outside of an interrupt. Because there is a write FIFO, can I assume that writes are atomic and don't require mutual exclusion? Inside the interrupt routine I will write to external addresses only. Outside, in the main loop, I will read and write to external adresses. If I read from outside the interrupt, and an interrupt occurs after the read cycle has commenced, will the correct value still be returned, on exiting the interrupt.

[waclawek.jan]

Answers are probably yes, but first of all you have to map FMC as Device in MPU, either by creating an appropriate area in MPU, our using the FMC remap.

JW