Flash memory status register EOP bit (end of operation status bit) datasheet not clear

[Brian D]

Re to document STM32F2xxx Reference Manual Rev1. Edited: STM32F72xxx

Under Flash register section, it says:

Bit 0 EOP: End of operation

Set by hardware when one or more Flash memory operations (program/erase) has/have

completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =1).

This is a status bit telling if program/erase is done or not, then why it is set only if the interrupt bit (EOPIE) is set? What if the user only polling?

Brian

[waclawek.jan]

You can use the BSY flag for polling.

JW

[Brian D]

So the Manual is wrong saying " It is set only if the end of operation interrupts are enabled (EOPIE =1)"? The trouble is that in addition to bit0 EOP, Bit 1 OPERR:Operation error also requires the same deal, that the corresponding interrupt bit is enable. These are FLASH_SR bits.

Could someone from STM confirm this and correct the error in the Manual?

Brian

[Piranha]

No, the manual is not wrong. EOP is bit 0 and BSY is bit 16. BSY does not need interrupts to be enabled.

As for OPERR documentation error.. So You are asking manufacturer to update documentation, but You don't use those updated versions and do not even check if they exist? ST has corrected it 8 years ago!

PM0059: STM32F205/215, STM32F207/217 Flash programming manual, Rev 2, 09-Dec-2010:

"Changed access type to bits 0 to 7 to rc-1, and OPERR description in Section 2.8.4: Flash status register (FLASH_SR)."

[Brian D]

Piranha,

I'm questioning bit0 and bit1: EOP and OPERR, and I did not question bit16 BSY. Please read the post again. Do you know why bit0 and bit1 of FLASH_SR are set only if their corresponding interrupt enable bits are set, as the Manual says? What is the logic behind this requirement?

I'm questioning the RM0431Reference manual Rev1 edited January 2017, not the PM0059 Flash Programming Manual 12/09/2010 (older date) that you referenced to. Who said the older PM0059 Rev2 superseed the newer Reference Manual Rev1?

Brian

[Tesla DeLorean]

The RM0431 doesn't relate to F2 series parts, no wonder everyone is confused.

State the exact part you're using. Guessing F722 but need to be specific. ​

[Brian D]

Sorry my bad. The document is STM32F72xxx Reference Manual (I missed the number 7 out). The part I'm using is STM32F722IEK6TR.

[Brian D]

Bump it up.

Does anyone know why the document says that the corresponding interrupt enable bits must be set in order for these status bits in the FLASH_SR to set?

Brian

[Piranha]

Well... because EOP and OPERR are not error type indicators but interrupt status bits! =)

When polling, after operation You must wait for BSY bit to be cleared and then check bits 4-8 (WRPERR, PGAERR, PGPERR, ERSERR and RDERR) for errors.

P.S. RM0431 is Rev 3 from 26-Jun-2018.

[Brian D]

Why the condition for setting bit0 and 1 is different than bit8? IOW, why they are not set the same way as bit8 and many other flag bits that are capable of generating interrupt?