Feasibility of design concept using extern adc + stm32 gpio + dma

[SYoon.1]

Hi,

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I am working on custom design using stm32h743zi with ad9269 16bit 20MSPS ADC. Since I am a newbie for this kind of design and I needed to consider all the analog & digital part at the early stage of design, I just simply connected the adc outputs (16 bits) to stm32h7's gpio ports at the beginning. Now I realized that this kind of configuration is so foolish, and I am now in trouble to read the fast switching adc outputs (20 MHz) from stm32h7 directly.

I understand the fundamental solution would be re-designing (e.g. add FPGA), but at least I want to try do something within current design. Now I think if it possible to read adc outputs for a certain time interval (e.g. 100 us) by suspending most of the stm32h7's functions during the read operation.

There is a data clock output signal (20 MHz) from ADC, which is also connected to one of the gpio pin of stm32h7. Based on external interrupt from this pin, I'd like to request DMA transfer from gpio pins (16 bit adc outputs) to SRAM (I found only EXTI0 is accessible for direct DMA request at CubeMX). I wonder this kind of thing is actually possible or just a silly idea.

• HCLK of stm32h7 ~ 380MHz, ADC data clock output = 20 MHz

I really appreciate for the any kind of comments.

Thanks!

Regards,

Seongjun

[AvaTar]

At least at 20Msps, this seems not the best idea.

I would consider attaching the ADC output to the external data bus (similar to external Flash/RAM), perhaps with some glue logic.

I never worked much with external memory devices, though.

Your next consideration should probably be how to process the 40Mbyte/sec troughput.

[SYoon.1]

Thanks for the advice! I guess the external data bus means an additional memory devices like FIFO something like this:

https://www.digikey.kr/product-detail/en/texas-instruments/SN74V293-6PZA/296-12491-ND/432044

Am I right?

It sounds great idea for my application, since I can store some adc outputs for a while, and transfer a bunch of data in the intermediate memory to MCU after. And it is suitable for my purpose. I am considering that kind of solution as well as FPGA, if I failed to utilize my current design.

Unfortunately, changing the hardware design is not viable for me at now. I wonder if it is still possible to transfer the GPIO pin read data to internal SRAM by DMA, where the ADC outputs are directly connected to MCU. I agree it is not the best solution, though.

Thanks!

[AvaTar]

Several discovery boards drive displays and external memory via the FSMC (ext. memory peripheral).

> Unfortunately, changing the hardware design is not viable for me at now. I wonder if it is still possible to transfer the GPIO pin read data to internal SRAM by DMA, where the ADC outputs are directly connected to MCU.

In theory, yes. But in practical terms, most probably not. You would need all 16 bits of one GPIO to properly access it via DMA. And you would still need a proper trigger for the DMA, to synchronize it with the ADC. Otherwise you end up with bit-banging, which eats significant parts of your core performance away.

I estimate the troughput of your ADC-to-memory solution as critical for your project, so attitudes like "changing the hardware design is not viable for me" might spell doom for it. I see a careful evaluation in order.