FDCAN Receive FIFO0 FIFO1 STM32H5

[DAUSILI]

Hi,
this is my MCU code: STM32H563VGT6.

I'm working to a porting from Texas to ST.
I need to efficently use the two Rx FIFO (3 messages depth) of the FDCAN module. In Texas I had 32 mailbox divided into transmission and reception.
Each FIFO has four buffer.
I need to accept all messages I receive.
I would like to find a way to fill FIFO 0 and then move to FIFO 1.
The only solution I found is to create two range filter: one for the first half part of IDs space assigned to FIFO 0, the second for the rest of IDs space assigned to FIFO 1.
In this way I'm going to overload FIFO 0 or FIFO 1, depending on the IDs that I receive.

There is a way to maximize the use of two receive FIFO ?

Thank you.
Regards.

[mƎALLEm]

Hello,

There is no way to balance the usage of FIFO0 and FIFO1 by the peripheral.

You need to estimate the reception throughput of each ID and try to assign these IDs to the FIFOs based on this throughput.

[MHoll.2]

mƎALLEm is right, You have to balance the load to the two RX FIFO's Yourself. But I'm normally using a Software Ringbufffer connected to the RX Interrupt, to prevent a hardware FIFO overflow. With this modern (fast) MCU's this has always work, even with very high bus loads (tested for example on a STM32G0B1x MCU (64MHz clock) at up to 500kBit/s, with nearly 100% load, and no Hardware filters).

If You really need a deeper HW FIFO, please consider the STM32H7xx familiy, they are configurable to have up to 64 RX Buffers.

Martin