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BjornLindholm
Associate II
June 20, 2024
Solved

FDCAN behaving differently on two identical stm32h735g-dk boards runnign the same code.

  • June 20, 2024
  • 3 replies
  • 1492 views

Hello,

I am running the code as shown in the attached file and I get two different behaviours on to identical stm32h735g-dk boards. One of the boards will send exactly 37 can messages when the button for master is clicked and the other board will send a infinite amount of messages. What could be the issue? 

Any help is welcome!

Kind regards,
Björn Lindholm

This topic has been closed for replies.
Best answer by mƎALLEm

Hello,

Not sure I understood well your issue. Each board having the same firmware but behave differently?

Also you are using an RTOS and this complicates the analysis. May be you need to test without RTOS.

Meanwhile, I have one comment regarding the bitrate config and mainly regarding these parameters:

 

 hfdcan1.Init.NominalPrescaler = 256;
 hfdcan1.Init.NominalTimeSeg1 = 2;
 hfdcan1.Init.NominalTimeSeg2 = 2;

 

 To me these are bad parameters and need to be changed:

TSEG1 and TSEG2 need to be increased as much as possible and decrease the prescaler as much as possible to fit your CAN bitrate where the sample point is at (70% to 80%) of the bit time. TSEG1 =~ (70% to 80%) (TSEG1+TSEG2 )

3 replies

mƎALLEm
mƎALLEmBest answer
ST Technical Moderator
June 20, 2024

Hello,

Not sure I understood well your issue. Each board having the same firmware but behave differently?

Also you are using an RTOS and this complicates the analysis. May be you need to test without RTOS.

Meanwhile, I have one comment regarding the bitrate config and mainly regarding these parameters:

 

 hfdcan1.Init.NominalPrescaler = 256;
 hfdcan1.Init.NominalTimeSeg1 = 2;
 hfdcan1.Init.NominalTimeSeg2 = 2;

 

 To me these are bad parameters and need to be changed:

TSEG1 and TSEG2 need to be increased as much as possible and decrease the prescaler as much as possible to fit your CAN bitrate where the sample point is at (70% to 80%) of the bit time. TSEG1 =~ (70% to 80%) (TSEG1+TSEG2 )

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.
BjornLindholm
Associate II
June 24, 2024

So the sample point must be above 70% for the can bus to behave "normally"? I am not too familiar with the can protocol so an explanation would be helpful :). Yes we are using the same firmware on two of the same model board and they are acting differently from one another.

Björn

mƎALLEm
ST Technical Moderator
June 24, 2024

Hello,


@BjornLindholm wrote:

So the sample point must be above 70% for the can bus to behave "normally"? I am not too familiar with the can protocol so an explanation would be helpful :). 


I suggest you to look at this link: http://www.bittiming.can-wiki.info/ for CAN sample point calculation sheet.

And also the following docs:

1- For classical CAN: http://www.oertel-halle.de/files/cia99paper.pdf

2- For CANFD: http://www.oertel-halle.de/files/icc14_2013_paper_Hartwich.pdf

 

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.