Posted on August 01, 2017 at 10:53Saving the area of the PCB - use two SPI interfaces on each chip. The first in master mode, the second in submission mode.
You can not think about clock synchronization. The delay will be minimal. It is important to understand, the chip that transmits information - uses the memory of a neighboring chip to store data. For this reason, the start of information exchange should occur by mutual synchronization of readiness. For example, on receiving / transmitting a number that increases on the other side.
The data exchange works through the ring buffer, the tail / head indicators are located in different parts of the access. The head pointer is read on its own memory, the tail pointer is located on the memory of a neighboring chip.
To use sets of flags is a useless occupation, tested by our own experience. Once the ideal balance is found, a new need for a fresh resource appears. This race is infinite, it just spends your time.
Without saving the PCB, an external chip, for example CY7C028-15AXC.
Work with ring buffer on external memory, without restrictions, without synchronization, without prohibitions and distortions of information. Everything is possible, except for a beautiful printed circuit board. A multi-layer printed circuit board is required - to hide the hinges.
Without saving a PCB, but with saving your own time.
Use an external FPGA chip to simulate two ported sram memory. This can be a simpler solution - than you think at first glance. After all, you have the opportunity to independently assign contact connections for the FPGA chip.
For debugging communication technology - use usart. When the software model is stable and fast - you can go to a faster interface. I'm not kidding.
