False Framing Errors?

[dibs]

Posted on August 03, 2014 at 23:35

I am using an STM32F407 to receive data via UART and seem to be getting false FE interrupts. There are two reasons why I believe that they are false:

1. I have looked at the timing on an oscilloscope and it appears to be fine.
2. If I disable the interrupt, I can receive the data intact with a passing CRC.

Specs:

USART6

1.8432MBaud (I have also tried 115.2kBaud)

8E2

    USART_InitStructure->USART_BaudRate              = BAUDRATE;

    USART_InitStructure->USART_WordLength          = USART_WordLength_8b;

    USART_InitStructure->USART_StopBits                 = USART_StopBits_2;

    USART_InitStructure->USART_Parity                     = USART_Parity_Even;

    USART_InitStructure->USART_HardwareFlowControl = USART_HardwareFlowControl_None;

    USART_InitStructure->USART_Mode                = USART_Mode_Rx | USART_Mode_Tx;

InitUSART(&USART_InitStructure);

USART_ITConfig(USARTx,USART_IT_ERR,ENABLE); 

Any ideas what conditions could be causing this?

#framing-error #stm32f4 #usart

[Tesla DeLorean]

Posted on August 04, 2014 at 01:13

Well you'd probably do better using a logic analyzer, and toggling a GPIO bit when you see the error, and then try to correlate the two.

Do you need 2 stop bits? Is the next start bit falling within the stop zone? Is it recognizing a glitch as a start bit, and then rejecting it?

[dibs]

Posted on August 12, 2014 at 14:23

After some looking, I have solved my problem. ST UARTS include the parity bit as the MSb in the data bits. So 8E2 needs to be set up with a 9 bit word, not an 8 bit word.

I am getting this information from RM0090 Rev6: CR1->PCE bit explanation

Am I correct in this assessment?

I did not expect this to be the case; I expected that the parity bit would be found after the MSb of what we call the data byte, not to be the MSb of the data byte. Is there a standard implementation for this?

[Tesla DeLorean]

Posted on August 12, 2014 at 17:05

Yes, 8-bit + parity is configured as 9-bit in STM32 implementation.

[dibs]

Posted on August 13, 2014 at 20:03

Do you know if this is a normal way of doing it or something strange the ST does?

[Tesla DeLorean]

Posted on August 13, 2014 at 21:01

I think it simplifies the silicon implementation. Others might mask it by having multiple bits documented to support 7N1, 7O1, 7E1, 8N1, 8O1, 8E1, etc or hidden it in the API.