Question
F7 QSPI issue
What kind of reason would the DR register read the same on subsequent calls in release build?
If I don't add __NOP()'s in there, the registers read the same and the FIFO doesn't get emptied.
Micro is STM32F769NI
static uint32_t drvInit(void) {
uint32_t i = 0;
struct {
uint8_t manId;
uint8_t memType;
uint8_t memCapacity;
} id;
NVIC_SetPriority(DMA2_Stream2_IRQn, PRIORITY_QUADSPI_DMA);
NVIC_EnableIRQ(DMA2_Stream2_IRQn);
NVIC_SetPriority(QUADSPI_IRQn, PRIORITY_QUADSPI_INT);
NVIC_EnableIRQ(QUADSPI_IRQn);
//Reset QUADIO if is quad IO currently
QUADSPI->CCR =
QSPI_CCR_INSTR(SPI_FLASH_RST_QUAD) |
QSPI_CCR_IMODE(QSPI_CCR_4LINES) |
QSPI_CCR_FMODE_IW;
while (QUADSPI->SR & QSPI_SR_BUSY_FLAG) {
};
QUADSPI->DLR = QSPI_DLR_COUNT(3);
QUADSPI->CCR =
QSPI_CCR_INSTR(SPI_FLASH_INS_RDID) |
QSPI_CCR_IMODE(QSPI_CCR_1LINE) |
QSPI_CCR_DCYC(0) |
QSPI_CCR_DMODE(QSPI_CCR_1LINE) |
QSPI_CCR_FMODE_IR;
QUADSPI->AR = 0;
while (!(QUADSPI->SR & QSPI_SR_TC_FLAG)) { //tc wait
};
id.manId = *(uint8_t *)&QUADSPI->DR;
__NOP();//<-- Nop required for DR
id.memType = *(uint8_t *)&QUADSPI->DR;
__NOP();//<-- Nop required for DR
id.memCapacity = *(uint8_t *)&QUADSPI->DR;
//Set to 4 BYTE address
QUADSPI->CCR =
QSPI_CCR_INSTR(SPI_FLASH_INS_EN4BYTEADDR) |
QSPI_CCR_IMODE(QSPI_CCR_1LINE) |
QSPI_CCR_FMODE_IW;
while (QUADSPI->SR & QSPI_SR_BUSY_FLAG) {
};
//Set to QUADIO
QUADSPI->CCR =
QSPI_CCR_INSTR(SPI_FLASH_ENT_QUAD) |
QSPI_CCR_IMODE(QSPI_CCR_1LINE) |
QSPI_CCR_FMODE_IW;
while (QUADSPI->SR & QSPI_SR_BUSY_FLAG) {
__NOP();
};
LL_DMA_EnableIT_TC(DMA2, LL_DMA_STREAM_2);
LL_DMA_EnableIT_TE(DMA2, LL_DMA_STREAM_2);
LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_2, LL_DMA_CHANNEL_11);
return id.manId == JEDEC_MAN_ID &&
id.memType == MICRON_3V_TYPE &&
id.memCapacity == MICRON_512Mb;
}