F427 - Timer interrupts right after start?

[hof2]

Posted on January 11, 2016 at 11:46

Hi Guys,

I am setting up my F427 with a master-slave timer (TIM4->TIM1). TIM4 triggers two capture and compare interrupts, CC2 (CCR2 = 1), and CC4 (CCR4 = 5000). TIM1 is triggered by CC2 signal. The behavior of the configuration is correct, unfortunately when I start the master-slave timer with:

/* start slave-timer */
if

(IS_TIM_ADVANCED_INSTANCE(TimSlaveHandle.Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(&TimSlaveHandle);
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(&TimMasterHandle);

the interrupts are triggered right after. In this regard I found this link

https://electronics.stackexchange.com/questions/161967/stm32-timer-interrupt-works-immediately

. If I debug, the UIF and the UE flags are cleared, but I still get the interrupts of CC2 & CC4. If I read the manual right (p. 520), this is the correct behavior. Am I right? In other words, when I start my PWM counter it immediately triggers an interrupt? Thanks you for your time and help. eimer #interrupt #flag #updat #interrupt #stm32 #stm32 #timer #timer #timer

[Radosław]

Posted on January 11, 2016 at 12:43

Generate update event by software before enabling timers.

[Walid FTITI_O]

Posted on January 11, 2016 at 15:39

Hi life_augmented.st,

This is not an intrinsic issue; not related to Timer peripheral but related to the way

TIM_Base_SetConfig(..) function is coded (called in HAL_TIM_Base_Init(..) ).

In fact, this function sets the update generation bit ( UG) which sets the update interrupt flag UIF, and an update interrupt is generated.

If a user, in a case like yours, want to customize and disable the generation of interrupt when setting the UG bit with keeping it coming only from counter overflow/underflow source, he should enable the URS bit in the TIM_CR1 register before calling the Timer base Init function :

/* Set the URS bit */ 
TIM1-> CR1 |= TIM_CR1_URS; 
/* Call Timer base Init */ 
HAL_TIM_Base_Init(..); 
/* Reset the URS bit */ 
TIM1-> CR1 &= ~ TIM_CR1_URS; 

-Hannibal-

[hof2]

Posted on January 13, 2016 at 13:29

Hi Hannibal & dembek,

Thank you for your quick reply. Your fix works like a charm for the problem I stated. Unfortunately, my problem shifted now. 

The issue is now, after I started the master once, stop the timer, and start it again, the first pulse is not generated at all. Only the next (second) pulse is generated. This is a strange behavior to me. 

On the other hand, if I set the UG-bit, the behavior is the other way around. 

This is really confusing me...

Thank you for your time and help, if anybody can point me in the right direction, that would be highly appreciated.

[hof2]

Posted on January 13, 2016 at 15:57

I need to take back what I said, I did make an mistake here. 

Setting the URS-bit is not protecting the f427 to throw an interrupt for CC2 or CC4. In fact it is changing anything for me.

On the positive side, if you want to resolve the issue with a pulse missing after a start-stop-start cycle, you simple need to reset the counter value of the timer. For me TIM4->CNT = 0.

I hope somebody can help, this felt solved and then the problems popped up again :(