F405 DMA1 configuration IMPOSSIBLE

[charles239955_stm1_stmicro]

Posted on April 26, 2013 at 17:00

Hello to all of you ST lovers,

I got a problem : working with ChibiOS (which includes the stm32 libs) I'm trying to enable some DMA actions (to capture a timer value, as it happens). Yet whatever I do in the DMA1 Stream2 Config Register (DMA1_S2CR) it remains at 0x 0000 0000 ... And same for the others I need (PAR, M0AR, NDTR).

Yes, I did enable the clock for DMA1, yes ChibiOS did enable the AHB clock from the PLL (which it plugged on HSE and yes I have an external quartz that works just fine). Yes I did make sure I disabled the DMA1 Stream2 and yes I did wait until the EN bit was actually zero (even though I'm in my initilization method and I bet that's all useless).

Is there anything else in the ''dumb basic things to do'' ? What could otherwise be the problem ?

I really badly need help, so thanks in advance for your help and insights !

Charles

#dma-chibios #stm32f405 #!impossible

[Tesla DeLorean]

Posted on April 26, 2013 at 17:54

Yet we are not presented with any initialization code... Magic 8 Ball says ''Try asking question again''

Unresponsive peripherals are almost always about clocks, or being held in reset.

[charles239955_stm1_stmicro]

Posted on April 26, 2013 at 18:03

My bad, there you are. I did not check ''being held in reset'', is that a reference to the RCC RST registers ?

// DMA REQUESTS

// TIM3_CH4 events are mapped to DMA1 Stream 2 channel 5


// Enable DMA1 clock (not low power)

rccEnableDMA1(FALSE);


// Disable DMA channel and wait for actual disabling

DMA1_Stream2->CR &= ~DMA_SxCR_EN;

while
(DMA1_Stream2->CR & DMA_SxCR_EN);


// Peripheral address : timer capture register

// (CC4, 4th element in stm32_tim_t CCR array)

DMA1_Stream2->PAR = (
int
)&(GPTD3.tim->CCR[3]);


// Memory address : array of times of each '1' bit received

DMA1_Stream2->M0AR = (
int
)ones;


// Number of data items per request : max 8 (will stop DMA transfer if less)

DMA1_Stream2->NDTR = 8;


// Channel to be used : channel 5 (write 101 in CHSEL of S2CR)

// Stream priority : middle

// Peripheral 'half word' (16 bits) data size

// (memory data size forced to peripheral data size on ENable)

// Memory increment mode.

DMA1_Stream2->CR |= DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC;

[Tesla DeLorean]

Posted on April 26, 2013 at 18:26

Seems to use it's own code, not the library. You could try a simple library test to confirm how the registers behave outside the OS.

You could also probe the RCC registers to confirm the current system state.