Question
Extra clock pulses with slow SPI master.
I wonder if there is some known issue?
With logic analyzer I confirmed that I had extra clock pulses in the SPI after the data was read.
The chip is STM32F427@180MHz.
PCLK2 is 90 MHz
SPI4 (master) is used with 16 bits and with prescaler 64, half duplex, single data line.
I'm reading two 16-bit words with HAL_SPI_Receive(), and after it returns, I turn NSS high.
What I saw with logic analyzer was that after NSS goes high, there were still 16 clock pulses coming out.
When I changed the prescaler even bigger (128), there were no more extra clock pulses.
The chip in the other end has 2 MHz maximum SPI clock.
More accurately:
- chip select LOW
- write 16-bit read command with HAL_SPI_Transmit()
- while receiver is not empty, read DR
- read two 16-bit values with HAL_SPI_Receive()
- chip select HIGH
- 16 extra clock pulses seen
