External timer clock source

[tg.developer]

Posted on February 27, 2014 at 21:21

Hi,

I am trying to use external clock source for TIMER via TIMERx_ETR pin. Timer is counting,

but I it looks like, that this clock is not feed to the timer counter directly and I am experiencing

''bad'' time period. My input clock is 32.768000Mhz from high stability TCXO. In this application note:

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00042534.pdf

is stated:

''

 

In these cases, the clock is provided by an external signal connected to TIx pins or ETR pin. 

 

The maximum external clock frequency should be verified.

 

In addition to all these clock sources, the timer should be clocked with the APBx clock.

 

The external clocks are not directly feeding the prescaler, but they are first synchronized 

 

with the APBx clock through dedicated logical blocks.

 

''

So the questions are:

Is my external clock too high?

External clock is somehow discharged and timer is clocked from internal clock after

synchronization taken place.

Could someone please explain this situation.

[Tesla DeLorean]

Posted on February 27, 2014 at 22:02

Too high compared to what?

The synchronizer gets the input into the AHB/APB clock domain for the pin/peripheral, it likely takes the input and samples it through a chain of 2 or 3 flip flops clocking from the domain clock you're entering.

Given you have two distinct frequencies, you'd expect it to add jitter, as the phase shifts back-and-forth depending on where the input edge occurs with respect to the internal clock. On an STM32F4 figure 84 MHz, 12 ns.

[tg.developer]

Posted on February 28, 2014 at 12:24

Too high compared to what?

 

In application note is written: The maximum external clock frequency should be verified.

So if I understand you correctly I can't get timer time base correct counting from my external

clock if not synchronized with internally clocks. 

[Tesla DeLorean]

Posted on February 28, 2014 at 16:12

Ok, but what part are you using, and what are you clock it and the buses at? ie ''Compared to What'' you provide only details of your input clock.

The clocking of the internal timer is NOT synchronous with your external source.

The input clock is effectively resampled (nyquist issues exist), and the external clock edges are moved to be synchronous with the internal clock edges. Depending on how the two frequencies interact, that's going to introduce a lot of phase noise, if counting over a long period this will get absorbed, but examining individual cycles it will look ugly.

You could drive the whole design with a single clock source, which things would then be synchronous with, but the max input clock is 32 MHz on some parts, less on others (25-26 MHz ?).