External SRAM issue

[ranran]

Hello,

I hope someone can help with this riddle.

We just started working with our custom board, based on stm32h743 (untill now we worked with eval stm32h743-eval board).

The internal memories, GPIOs and other interfaces works OK, but we have the following strange issue with the external sram:

In our test we write 0x400 bytes (0x200 16-bytes words) and read these 0x400 bytes and compare values.

1. Reading from sram immediately after writing works OK, ( we get the same values we have written for all the 0x200 16-bytes words), but if we stop at breakpoint and open memory debugger for addresses starting from 0x68000000 just after the reading and do a step , then the memory in 0x68000000 .... changes from the correct written values to 0xfffffff ....
2. We suspected that it is issue of debugger view of memory, but we see similar behavior even if we close all memory views: when we just toggle a led after the reading, and do again a reading of 0x200 words we then see that only some values inside the 0x400 bytes in sram changed from the correct written value to 0xffffffff.
3. We use CY7C1061GE30 (https://www.cypress.com/file/46676/download)
4. These are the timing we use (we use the maximum "slow" timing):

SRAM_Timing.AddressSetupTime = 0;
 SRAM_Timing.AddressHoldTime = 1;
 SRAM_Timing.DataSetupTime = 1;
 SRAM_Timing.BusTurnAroundDuration = 0;
 SRAM_Timing.CLKDivision = 16;
 SRAM_Timing.DataLatency = 17;
 SRAM_Timing.AccessMode = FMC_ACCESS_MODE_A;
 g_hsram.Init.NSBank = FMC_NORSRAM_BANK3;
 g_hsram.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
 g_hsram.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
 g_hsram.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
 g_hsram.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
 g_hsram.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
 g_hsram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
 g_hsram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
 g_hsram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
 g_hsram.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
 g_hsram.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
 g_hsram.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
 g_hsram.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;

 It "feels" as if some code action interrupt the sram conmtroller timing. Does it make sense ?

Thank you for any idea,

ran

[Tesla DeLorean]

Sounds more like the data never actually gets written, and you just see the data in the caches, until it gets replaced.

[ranran]

Right!

I now see that it gives 0xfffffff in all reads.

What does it mean ?

[ranran]

I also suspected this, but I have configured 0x68000000 as non-cacheable in MPU.

MPU_InitStruct.Enable = MPU_REGION_ENABLE;
  MPU_InitStruct.BaseAddress = 0x68000000;
  MPU_InitStruct.Size = MPU_REGION_SIZE_64MB;
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
  MPU_InitStruct.Number = MPU_REGION_NUMBER3;
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
  MPU_InitStruct.SubRegionDisable = 0x00;
  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
  

 Is something wrong with this configuration ?

Thank you