External LSE clock tr/tf is lower than tr/tf of external HSE clock

[jp1]

Posted on May 21, 2018 at 08:03

We would like to know if there's a typo for tr/tf (10 ns max) of OSC32_IN in the following STM32L151x data sheet table:

The reason we believe the above tr/tf value is a typo because the tr/tf for a high speed clock is twice as long(20 ns max) :

We are trying to feed an external 1.8V swing 32.768 kHz clock in to OSC32_IN from a micro power oscillator which can only support rise/fall times of 30 ns.

Will this work?

Thanks,

JP

#fall-time-stm32l1 #osc32_in #rise

[Imen.D]

Posted on May 24, 2018 at 12:18

Hello

Parvereshi.Jehangir

,

In external clock mode the LSE input is a simple logic gate without hysteresis.

To avoid glitch in this mode, it is better to use a fast transition signal. This

is the reason why it specified 10ns for LSE.

The situation for HSE is different since in external clock mode there is ahysteresis and the input signal can be slower.

You can

try and check the glitches in your specific application, but we will not guaranty anything on our side.

Best Regards,

Imen

[jp1]

Posted on May 29, 2018 at 18:43

Hi Imen:

I would think that for a slower clock rate a slower transition should be allowed.

Looks like ST had decided to implement hysteresis on a faster clock input and not on the slower clock inputs.

Thanks for the confirmation.

TimeIT