Embedded SRAM (Cache) Organization for STM32F429ZIT6U MCU

[sakibi15]

Posted on October 16, 2015 at 07:41

Hello,

I am interested in knowing the physical memory organization for the embedded SRAM (cache) for the STM32F429ZIT6U core which is utilized in a STM32F429I-DISCOVERY Board.

The memory map within the global address space says that 192 KB of data can be accessed between addresses 0x20000000 => 0x20030000. I believe the memory is byte-addressable [32-bit address corresponds to 1-byte or 8-bits of data], and that the wordsize is 32-bits, since this MCU is based on the ARM Cortex M4. Is this all correct?

For e.g., is the memory organized as a matrix where each row contains 4 words, is the memory interleaved, is there any special aspect of the physical organization? I have the reference manual at hand, I wasn't able to find the cache organization. This is for the performing of running data analytics and statistics on the memory profile upon successive power-ons. Any help is sincerely appreciated.

[waclawek.jan]

Posted on October 16, 2015 at 11:44

> Is this all correct?

Yes.

While from usage standpoint the SRAM is partitioned into 3 parts connected to 3 different slave ports of the interconnect bus matrix, there is no implication from this fact to the actual physical layout (although it's quite likely there are 3 separate areas on the silicon occupied by the SRAM).

> For e.g., is the memory organized as a matrix where each row contains 4 words, is the memory interleaved, is there any special aspect of the physical organization?

This information is not made public, as it's not needed to use the chip. ST may change the layout without notice if all datasheet parameters remain unchanged.

I suggest you to contact ST through the request for support form on their web or through their FAE, and support your question with a VERY GOOD explanation of why do you need that information (e.g. research or diploma work, giving links to your academia etc.).

Oh, and I wouldn't call it cache.

JW

[jpeacock]

Posted on October 16, 2015 at 17:48

Unlike the Cortex A series embedded SRAM cannot be used as an L2 cache on Cortex M controllers.  The SRAM is banked but not in the same way as DRAM.  Banks refer to bus matrix ports and determine when simultaneous transfers can occur, for example CPU accesses the TCM SRAM (not on matrix) while DMA1 accesses SRAM bank1 and DMA2 accesses SRAM bank 2.  Look at the 'F429 reference manual in the bus matrix section.

You are looking at memory benchmark terms for a server.  Embedded controllers have a different memory architecture so you have to look at the overall IC layout, especially the bus matrix, flash lookahead accelerators and (for the M7) I and D cache.  Since bus transfers through the matrix can occur in parallel you have to define thruput in terms of what an application does in managing DMA transfers plus tight coupled memory management.

  Jack Peacock

[sakibi15]

Posted on October 16, 2015 at 23:04

Thank you sincerely for your reply.

My apologies for misinterpreting - the embedded SRAM memory is not a cache, it's the main memory for the MCU. 

The SRAM is indeed broken into 3 parts, 112 KB, 16 KB and 64 KB [SRAM1, SRAM2, SRAM3].

I will contact ST accordingly regarding the physical IC layout of the SRAM. I'm a graduate student in VLSI and I require this information purely for research/academic purposes.

[sakibi15]

Posted on October 16, 2015 at 23:08

Thank you sincerely for your reply.

I was under the impression that memory systems, regardless of the computer system (desktops, mobile phones, embedded systems, etc.) share similar terminology when it comes to describing the physical organization. Are you referring to the banks of SRAM: {SRAM1, SRAM2, SRAM3} = {112 KB, 16 KB, 64 KB}?