ECC on STM32H7 - L1 caches - How to check the ECC bits

[MDomo]

​Hello,

i am trying to figure out how to read out the ECC Status for the L1-Cache of a STM32H743 Microcontroller. I managed to find out how to enable or disable ECC in the instruction and data Cache but I cannot find the place from where to read out an eventual Cache error.

Did anyone manage to do this? Or is there any documentation I am missing?

Thank you in advance!

Best regards,

Mihai Dömötör

[Tesla DeLorean]

As I understand the mechanics you need to decode ABFSR when it bus faults

http://www.keil.com/appnotes/files/apnt209.pdf

[CHead]

I think you want DEBR0/DEBR1/IEBR0/IEBR1. See the Cortex-M7 technical reference manual.