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mjohansson
Associate II
September 15, 2008
Question

Doing a reset

  • September 15, 2008
  • 4 replies
  • 1704 views
Posted on September 15, 2008 at 07:13

Doing a reset

    This topic has been closed for replies.

    4 replies

    mjohansson
    Associate II
    May 17, 2011
    Posted on May 17, 2011 at 12:44

    Hello everyone!

    I'm using IAR EWARM 5.11 a j-link and a STM32F103VBT6 processor. I've been trying to do a reset. I've tried iwdg, the sysresetreq bit and the hw way by nrst. And they all have a common behaviour, I end up at the HardFault vector. The vector table checks out, the boot0 pin is 0, so, what am I missing?

    mjohansson
    Associate II
    May 17, 2011
    Posted on May 17, 2011 at 12:44

    Sorry everyone.

    Of course it was programmer error in low_level_init(). :-?

    trevor1
    Associate III
    May 17, 2011
    Posted on May 17, 2011 at 12:44

    A good way to reset from software is like so (from the ST firmware library).

    Code:

    /*******************************************************************************

    * Function Name : NVIC_GenerateSystemReset

    * Description : Generates a system reset.

    * Input : None

    * Output : None

    * Return : None

    *******************************************************************************/

    void NVIC_GenerateSystemReset(void)

    {

    SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;

    }

    mjohansson
    Associate II
    May 17, 2011
    Posted on May 17, 2011 at 12:44

    Thanks. But that was what I meant by ''the sysresetreq bit''.

    Still having problems with the reset though, still might be programmer error but I can't find it. It happens when the MCU is switched over from HSI to PLL systemclock. Starting it up once by JTAG works but when doing a reset or running standalone I end up at the HardFault vector when doing the switch from HSI to PLL for system clock. The PLL clock is generated from a HSE clock input (HSEBYP bit set to 1). The RCC_CR and RCC_CFGR both look the same for the first startup and the reset. So what might be different that I'm not noticing?