Does STM32H7xx SPI driver support adding delay between SCK and SS signals?

[RKolo.2]

Usually peripherial SPI drivers support 3 delays to control signals timing:

1. Delay from SS enable edge to first SCK edge (SS Idleness) - supported in STM32H7xx
2. Delay between data (Inter-data Idleness)- supported in STM32H7xx
3. Delay after SCK edge to SS disable edge (ASC in the picture) - seems to be not supported.

 

Does STM32H7 SPI support the third delay?

If not then, what is the value of it and does it depend on anything?

Can it be modified directly or indirectly by a different attribute?

[waclawek.jan]

The SPI module in the 'H7 is overcomplicated, but not that much as you'd expect, see the SPI chapter in RM. It simply inserts a SS pulse of SPI_CFG2.MSSI lenght between frames, and RM/DS are not clear about its exact positioning.

If you want more precise control, you may want to generate SCK+SS e.g. using a timer, and loop it back externally to SPI set as slave.

JW

[Wall-E]

The third delay is not programmable, it is fixed to one SCK period.

As you can see from the timing diagram below (extracted from the STM32H7 reference manual), in "Motorola" mode the SS signal goes inactive one SCK period after the last active edge of SCK (rising or falling depending on the CPHA and CPOL bits in the SPI_CFG2 register) and stays inactive for one less SCK period than the inter-frame gap specified in SPI_CFG2.MIDI[3:0].

Figure 775. SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0)