Does SDRAM freq 100MHz mean 10ns each clock or 10high and 10low = 20ns

[Dat Tran]

Hi everyone, I am a bit confused about this.

In STM32CubeMX tool, I configured SDRAM 100MHz, the tool GUI shows result 100MHz as well, then I generate code then test.

I check SD clock pin, it is 10ns on each single clock, no matter the clock is high or low, seems I config it correctly.

But if we say frequency is one lock high and one clock low (or same as PWM), mean currently SDRam runnng only 50MHz (one high + one low = 10 + 10 = 20ns => 50MHz).

So, in STM32H743 datasheet says maximum SDRAM 100MHz, is this 100MHz only one clock 10ns, no matter high or low, or this is a combination of one high and one low (5ns each clock)?

Many thanks,

 

[Tesla DeLorean]

Perhaps diagram what you are seeing, specifically, and with respect to other address, data or control signals.

I'd expect a 50/50 duty cycle with a period of 10 ns, with sufficiently aggressive edges.

The timing units of other signals should be in multiples of 10ns, ie relationships for RAS / CAS etc, and most memories furnishing responses with 6-7 ns

The burst data transfer rate should be measurable. SDRAM has a relatively large amount of overhead in small random transactions.

[Dat Tran]

"...I'd expect a 50/50 duty cycle with a period of 10 ns, with sufficiently aggressive edges..."

Can I understand SDRAM 100MHz should be mean 5ns + 5ns low = 10ns total?

Because 20ns seem to be very slow as I see.

[Tesla DeLorean]

Would suggest code that unpacks RCC clocks, SYSCLK, AHB, APB and PLLs and then to the FMC/SDRAM settings. Review the clock chain.