Does HyperRAM require terminations?

[shffhsdfhse]

I'm having trouble figuring out if an STM32H7 needs terminations for a HyperRAM memory. The memory I'm using has variable drive strength on the HyperRAM side, so I won't need terminations for RAM->MCU direction.

However, I can't find any information if I need terminations for MCU->RAM signals. I looked at some of the demo kits, and some don't have any terminations, and then others only have the source-series terminations only on the HyperRAM side (STM32H735G-DK). This would lead me to believe that I don't need terminations for MCU->RAM signals.

I've tried to do some simulations using the provided IBIS models, and the waveforms look pretty ugly, but I'm questioning the accuracy of my simulation and don't really trust them. I was hoping someone has some practical or real world information about terminations for these devices.

Also, do the data and clock lines use the regular GPIO buffers or do those pins have some special hardware?

I'm running both the HyperRAM and MCU at 1.8 V.

[Tesla DeLorean]

>>Also, do the data and clock lines use the regular GPIO buffers or do those pins have some special hardware?

Regular IO cells there, but you can impact the slew-rate/drive via SPEEDR setting, and generally one can ease back on those with short-trace/low-load situations.

The 33R or 27R in the lines (midway), like the H735G-DK, certainly something I'd seriously consider with signals pushing north of 66 MHz, if it were below 33 MHz I wouldn't bother. Just had so many headaches over the years with people skipping them and having all kinds of ringing issues.

[shffhsdfhse]

I already did some testing with the simulations and adding the resistor in the middle did seem to greatly improve the signal quality. I might try to add them to the board just in case.

However, the H735G-DK doesn't have the resistors in the middle, it has them touching up against the RAM IC. This is part of my confusion. I assumed that they either made a mistake, and it just happened to work, or there was something I was missing from the documentation or didn't understand.

Furthermore, the traces I am simulating on my board are less than 0.7 inches and looking ugly, but the traces on the demo kit are over 2 inches long, with vias, and apparently still work unterminated?

[Tesla DeLorean]

Well I think the placement is more of a convenience thing, vs the escape task from the BGA.

The inherent resistance of the trace is going to drop as it grows shorter.

[Alex - APMemory]

Hi,

Usually terminations are not required for any type of OPI

At least all test done with APMemory IoT RAM on STM32 platforms are without termination

Alex