does dual-bank read-while-write work properly in stm32l071?

Question

Posted on August 03, 2017 at 10:36 I'm trying to reprogram the NVM (flash bank 2) while running code from flash bank 1 in STM32L071CB microcontroller.  As AN4808 and AN4767 stand, 'the memory interface is capable of reading both banks in parallel, or reading one bank while writing to the other...' but I'm experiencing some problems:  Debugging shows that FWWERR bit goes high in the flash status register during flash bank 2 half-page write operation. It means that writting flash bank 2 has been stopped because of code fetching.Erasing bank 2 by code in bank 1 works properly.Writting by words bank 2 by code in bank 1 seems to work properly (but I'm having doubts if its only coincidence).Half-page writting ends with FWWERR bit set in FLASH_SR and zeros in the memory I'm trying to write.  I know I'm missing something but I can't find out what it is. Maybe someone had similar problem? I'm starting to think that there's something is wrong with the uC (errata sheet points out some problems with dual-bank switching mechanism, but it shouldn't be a problem in my case, because I'm not switching banks right now).  My function works properly when executed from RAM memory, but I'd rather want it to run from flash bank 1.  (you can take a look at the code here:  https://electronics.stackexchange.com/questions/321863/does-dual-bank-read-while-write-work-properly-in-stm32l071 )  SYSCLK is 16 MHz, checked on MCO with oscilloscope. PWR is in range 1 (the highest applicable).  Thanks for any help.  #flash-read-and-write #stm32l071 #dual-bank #firmware-update 
 Note: this post was migrated and contained many threaded conversations, some content may be missing.

Brian TIDAL · Accepted Answer

Posted on September 19, 2017 at 16:43Hi,Reading-While-Write has some limitation in case of Multiple programming operation. See http://www.st.com/content/ccc/resource/technical/document/reference_manual/21/bd/0f/bd/1c/88/40/f0/DM00108282.pdf/files/DM00108282.pdf/jcr:content/translations/en.DM00108282.pdf § 3.3.4 Writing/erasing the NVM - Program half-page in Flash program memory page 82:'When a half-page operation starts, the memory interface waits for 16 addresses/data, aborting (with a hard fault) all read accesses that are not a fetch (refer to Fetch and prefetch). A fetch stops the half-page operation. The memory content remains unchanged, the FWWERR error is set in the FLASH_SR register.'This means that no fetch operation are allowed in the flash while feeding the memory interface with the 16 words (whatever the code is running in bank 1 and the half page programming is performed in bank 2) . Once the 16 words have been sent to the memory interface, you can resume execution from flash, i.e. during the physical writing of the data inside the flash bank (assuming your code is running in the other bank).  In a nutshell, you need to execute from SRAM the feeding of the memory interface with the 16 words and make sure the interrupts will not cause fetch in flash memory (either mask all interrupts or relocate interrupt handlers and interrupts vector in SRAM).Note: there is no such limitation in case of Single programming operation.RegardsBruno

Tesla DeLorean · Answer

Posted on August 03, 2017 at 14:06Make sure you know exactly what part you are working with, and what die is inside. ST has had a somewhat liberal policy to die/marking, so while I think the part should act like a 128KB one, it might not.If the die has 192 KB of FLASH the second bank starts at 0x08018000 rather than 0x08010000Try your test at 0x08018000

Sign up

Login with SSO

Login to the community

Login with SSO

Scanning file for viruses.

This file cannot be downloaded