Does anyone have a clean example of SPI slave initialisation code

[Paul UHS]

Posted on May 25, 2010 at 09:37

Does anyone have a clean example of SPI slave initialisation code

[Paul UHS]

Posted on May 17, 2011 at 13:52

Thanks for your response.

You have confirmed what I thought about MOSI and SCK being alternate function pins. In the Reference manual it makes reference to this, but code that I managed to find on the net had these pins as inputs.

Thanks for the interupt pointers, I had managed to copy and paste code incorrectly from somewhere and was configuring SPI2 (note the 2), not 1.

Yep had the clocks up and running, but once again, glad you added this.

The CSS pins seems to be correctly toggling from the point of view of the CRO. I think I might have been having more issues from the things above instead of the CSS.

The CPOL/CPHASE should be inline with my master from what I believe, again I think it was more a combination of the problems above. But always good to check this. I actually thought this is where my problem was going to be.

Thankyou for the list of examples, this is what I have been searching high, and low for. Its been a while since I have had to look at those examples, and I couldn't for the life of me find those peripheral examples.

Thank you for the great response, I'll let you know how I go. I am re-working my master implementation on an FTDI chip that had a bug in it with the clock switching between NEG edge triggered and positive edge triggered.

[chikos332]

Posted on May 17, 2011 at 13:52

Hi,

From my side, I've always used the MOSI and SCK pins in AF_PP mode not in IN pull up mode. I don't know if it is the mode recommended by ST but it works fine for me.

Except this ''minor'' point, are you sure that you configured correctly the NVIC to enable the SPI interrupt ?

  NVIC_InitStructure.NVIC_IRQChannel = SPI1_IRQn;

 

  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;

 

  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;

 

  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

 

  NVIC_Init(&NVIC_InitStructure);

if you did it, then try polling mode first..

Do you enable the GPIOA and SPI1 clocks:

 

  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |                                                 RCC_APB2Periph_AFIO |                                             RCC_APB2Periph_SPI1, ENABLE);

Are you also sure that the CSS signal is correctly toggled to enable the slave operations ? (try the ''SPI_NSS_Soft'' mode as a start to have less complications)...

One other point: You have to check that the CPOL/CPHASE parameters are inline with your master (thus the default state of SCK should be the same for the master and slave and the active edge as well).

And finally, did you checked the ST provided example?

http://www.st.com/stonline/products/support/micro/files/stm32f10x_stdperiph_lib.zip

then go to folder STM32F10x_StdPeriph_Lib_V3.3.0\Project\STM32F10x_StdPeriph_Examples\SPI\Simplex_Interrupt

and remove all code relative to master then change SPI2 by SPI1...

I hope these remarks could help.

[chikos332]

Posted on May 17, 2011 at 13:52

Happy for you :)

You're always welcome :)

[Paul UHS]

Posted on May 17, 2011 at 13:52

Sending & receiving is working 100%

Thanks for your help.

The bug was in my interrupt service routine not being initialised in the NVIC, along with a bug in my master code, making my bits be shifted as the clock was changing between CPOL=1 and CPOL=0.

[septijo]

Posted on August 08, 2013 at 20:07

Dear chikos,

i need a woking example / step by step tutorial for STM32F0 SPI Slave, been searching for days with no luck.. do you / anyone here have any ?

thanks before

[Amel NASRI]

Posted on September 12, 2013 at 16:49

Hi Septi,

There are some example under STM32F0xx_StdPeriph_Lib_V1.0.0\Project\STM32F0xx_StdPeriph_Examples\SPI that may help you.

Of course, you have to download the firmware library package from the ST web site.

-Mayla-