Does a bigger DMA (I2S) Receive Array result more calculation time?

[akosodry]

Posted on March 11, 2017 at 12:00

Hello.

I am working on a project where i collect the external ADC results through the I2S peripheral (using double buffer DMA).

The algorithm works in the following way:

- Once memory 0 is filled, interrupt occurs, a flag is set, and in the while loop i execute a processing algorithm on the memory 0 data

- Then if memory 1 is filled, again interrupt occurs, flag is set, and in the while loop i process again the memory 1 data

The aforementioned algorithm worked fine so far. However, recently i implemented some higher order filters and i realized that the mcu doesnt have enough time. Namely, for example, the flag related to 'memory 0 is filled' event is set before the processing have been finished on memory 0 data.

I am curious, does the array size could affect the idle time of the mcu?

Or the other way around: Could bigger arrays solve this issue?

Currently the array size is:

&sharpdefine ADC_REC_DATA16_NO 600

this number is given to the HAL_I2S_Receive_DMA function with the corresponding arrays.

I hope the question is clear.

Thanks for the help in advance.

Best regards, �kos

#dma-spi-rx-receive #i2s #dma-i2s

[waclawek.jan]

Posted on March 11, 2017 at 12:22

If the processing algorithm scales (i.e. it's execution time increases) linearly or faster with number of data, then no, increasing buffer size won't help.

Sort of self-explanatory, isn't it.

JW

[S.Ma]

Posted on March 11, 2017 at 13:57

In the interrupt, check if the flag is already set then while 1.

Else set the flag and wait main loop to clear it.

You could try to speed up your computation or use half transfer interrupt. Increase sysclk or lower your incoming bit rate.

[Tesla DeLorean]

Posted on March 11, 2017 at 15:56

Larger buffers tend to increase the latency for doing the computation, you have to weigh that against efficiencies of doing more calculations at once from an algorithmic/caching perspective.