Separate between "word size" and "frame size". SPI can support "word size" as 4, 8, ... bits per word (up to 32bit).
So, 20bit as "word size" should be possible. If not directly, consider it as sending a 16bit word plus a 4bit word.
"Frame Size" is independent of it: if you can send any "word" (as 20bit) - any number of words can be transmitted (limitation is potentially on a 64K word size boundary, e.g. due to DMA addresses).
even SPI would not support 20bit word size - but MCU would provide a QSPI - the 20bit is possible via QSPI - but just as transmit only ("half-duplex"):
Configure a QSPI as 4-bit-lane but you use just one lane (only DIO0 = MOSI, for instance, is connected). Now you have two clocks per one byte. But you send all bits properly encoded in bytes (e.g. bit 0 and bit 4 Tx containing data bit 0, bit 1, etc.).
Now you have Nx 2 clocks (2 bits) you can send.
Just: such a QSPI is not full-SPI: it cannot run in "full-duplex" mode (MOSI and MISO at the same time). As long you need just a SPI Tx - you can use also a QSPI peripheral. (but I think you need SPI in "full-duplex", Rx when Tx - so, find MCU with 4..32bit SPI and configure it properly)