DMA with read strobe but without write strobe

[jasonp4113]

Posted on May 19, 2014 at 03:47

Hi All

STM32F2xx:

I assume this is not possible but....

Can a DMA transaction have the read strobe only without the write strobe (ie half the transaction)?

The reason is due to our project having an FPGA being mapped onto a SRAM bank.

Therefore to DMA from external memory into the FPGA, we need to read into the STM then write out again to the FPGA.

If we can use just the read-half of a STM DMA transaction, the STM nOE can be used as the nWR strobe into the FPGA - this then doubles bandwidth.

(The other option is to have the FPGA also as a DMA master loading directly from SRAM, but that introduces timing/contention complexities and defeats the purpose of already having a DMA master in the STM)

Thx

Jas

[waclawek.jan]

Posted on May 19, 2014 at 08:32

I don't quite understand what is your problem, but if you are unhappy with an external-to-external memory transfer, you can try to make it external-to-internal SRAM, with not incrementing the target.

JW

[jasonp4113]

Posted on May 20, 2014 at 00:59

Sorry if unclear:

The STM, some external memory and the FPGA share a common FSMC bus.

When the STM performs a DMA transaction, the DMA performs a nOE, nWE, nOE, nWE... sequence

I can easily inform the FPGA to detect and interpret the nOE strobe from the STM as the ''write enable'' to the FPGA to latch the data directly from the FSMC D-bus.

(In essence you are connecting the nOE of the STM to the nWE of the FPGA)

This effectively doubles transfer bandwidth but only if you can eliminate the nWE ''half'' of the transaction from the STM.

i.e. can you inform the DMA of the STM only to perform: nOE,nOE,nOE instead of nOE,nWE,nOE,nWE?

Cheers

Jas

[Tesla DeLorean]

Posted on May 20, 2014 at 01:58

Yeah, I don't think you can do a one sided transaction, so you'd need the DMA to sink the write some place else. Perhaps you could point it at some innocuous location in the peripheral space, like some unclocked GPIO bank, like one beyond the pin limits of your device, GPIOI ? Or non incremented SRAM address.