DMA underrun and overrun

[n.serina]

Hello,

Thanks for wonderful support

I am working on STM32F407X mcu DMA program and want to understand when will DMA underrun and overrun happens. This is not explained in any of the ST documents even though the RM mentions this

>>>>>>>>>

When burst transfers are requested on the peripheral AHB port and the FIFO is used (DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to avoid permanent underrun or overrun conditions, depending on the DMA stream direction: If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16. This rule ensures that enough FIFO space at a time will be free to serve the request from the peripheral.

>>>>>>>>>>>.

I wan to understand how using FIFO_Threshold = 3/4 when (PBURST × PSIZE) = FIFO_SIZE results in overrun or underrun. in which direction underrun happens ?

Thank you very much

[TDK]

> I am working on STM32F407X mcu DMA program and want to understand when will DMA underrun and overrun happens.

Underrun/overrun happens when the DMA is unable to service the request fast enough. This happens because there is limited bandwidth available to shift data around, and there can be contention for these resources between different parts on the chip. For example, converting ADC at the maximum sample rate and saving it to memory via DMA is going to tax the DMA bus heavily. If you do this, and also use the bus for other things, and underrun can occur if a new ADC conversion happens but the old data has not yet been shifted out by the DMA.

The note in the RM is just telling you about an invalid configuration. It's not really about overrun/underrun.

[n.serina]

Hi TDK,

Thank you very much for your help .