DMA Priorities and Associated Latencies

[brianvenus9]

Posted on September 03, 2010 at 21:56

DMA Priorities and Associated Latencies

#dma

[brianvenus9]

Posted on May 17, 2011 at 14:05

STOne-32:

Thank you for the response and the link to the document.  It appears that with 2 DMA channels, the highest priority DMA has to wait for the bus to clear before beginning its own transfer leading to a variable jitter time for DMA completion.

The only time DMA is entirely predictable is if there is only 1 DMA channel configured. 

[Nickname12657_O]

Posted on May 17, 2011 at 14:05

Dear Brian,

You will find all details on STM32F10xx DMA in

http://www.st.com/stonline/products/literature/an/13529.pdf

: Using the STM32F101xx and STM32F103xx DMA controller :

• This application note describes how to use the STM32F1xx direct memory access (DMA) controller. The STM32F1xx  DMA controller, the Cortex™-M3 core, the advanced microcontroller bus architecture (AMBA) bus and the memory system contribute to provide a high data bandwidth and to develop very-low latency response time software.

• It also describes how to take full advantage of these features and ensure correct response times for different peripherals and subsystems.

For latency , you can refer to Section 3  : Performance considerations

Ciao,

STOne-32.