DMA Overhead (ADC to RAM)
STM32F446 in my case...
When the ADC finishes a conversion and the DMA controller deposits the converter data into memory, what is the overhead ? i.e. How long does it take ? Is this shown in the documentation anywhere ?
I would assume that as soon as the A2D conversion is done, the DMA is triggered and if the RAM address and data bus is free, the DMA controller takes over, deposits the value and releases the busss and that's it. Is that correct ?
And why are interrupts generated ? I would think this could all happen without an interrupt taking up more resources ? CUBE added all that for me.
I do notice that at least for ADC1, commenting out the two interrupt lines did not keep the converted data from appearing at the correct locations as far as I can tell.
Still working on getting ADC2 and ADC2 going with their 2 or 3 streams. ADC1 values are getting screwed up when I enable those but I think I'm making some progress to that goal.
Thanks
