DMA misunderstanding (burst, data alignment, FIFO)

[BILLyTheLiTTle]

While I was reading a book about DMA I came up with some questions. I tried reading AN4031, RM0090 with no better luck in understanding.

The problem has to do about bursts in DMA. The questions are theoretical and there is no source code to follow them and some of them could be technically wrong,

Question 1:

In case of memory-to-peripheral communication I have to setup MSIZE and MBURST. In case of peripheral-to-memory communication the "Table 48" at pg318 of "RM0090" changes to PSIZE and PBURST?

Question 2:

In case the memory transfer data size is word aligned, the peripheral is byte aligned and "FIFO level = full", the DMA would burst:

• 1 burst of 4 beats in a memory-to-peripheral?
• 4 burst of 4 beats in a memory-to-peripheral?

Question 3:

In case of "FIFO level = 3/4" with "MSIZE = Byte" and the memory puts in FIFO exactly 1 byte of data. In this case the FIFO is not near the threshold of 3/4. Would any flush happen or the data would stay in FIFO?

Thank you in advance.

[TDK]

> In case the memory transfer data size is word aligned, the peripheral is byte aligned and "FIFO level = full", the DMA would burst:

It would generate 4 bursts of 4 beats (so it reads 4 words from the memory address and writes a total of 16 bytes to the peripheral address). Figure 39 helps explain this, although it doesn't cover this exact scenario.

> In case of "FIFO level = 3/4" with "MSIZE = Byte" and the memory puts in FIFO exactly 1 byte of data. In this case the FIFO is not near the threshold of 3/4. Would any flush happen or the data would stay in FIFO?

Nothing would happen until the FIFO threshold is reached. Use direct mode if you don't want this behavior.