Associate III
June 8, 2021
Question
DMA line output is one more cycle than expected
- June 8, 2021
- 3 replies
- 1349 views
Hi,
I'm trying to control multiple PWM signals simultanously using DMA (used for controlling LED drivers). However I'm having an issue I can't seem to trace, one of the lines puts out an additional PWM signal cycle that shouldn't be there, this is weird since all the lines are basically using the same routines and interrupt functions. I've added screenshots that should explain it better. The output is associated with Tim1_Ch1, DMA2_St1 which isn't the lowest priority of the used streams (so it can't be due to some interference delay).
My code can be found here: https://github.com/maksimdrachov/F429-UCS5603A
(All the most relevant functions can be found in /Core/Src/ucs5603a.c)
Anyone an idea what could be the cause of this?
