DMA based SPI communication with NSS

[mstuehn]

Posted on March 06, 2012 at 13:40

Hello,

while studying the STM32F4xx datasheet i found the following passage:

25.3.1: ''The NSS signal is driven low when the master starts the communication and is kept low until the SPI is disabled.'' 

 

This leads me to the conclusion, that it is nearly impossible to use SPI in conjuction with DMA. At least, if you need to deselect a slave-part after each transmitted word/byte. This is the case for my application, where an adc gets read out via SPI. It needs to be deselected and selected to start a new conversion. Does anybody know, how this could be realized with the STM32Fxxx? A pure sw-solution is possible, but it would be great using DMA instead of CPU/IRQ to copy the data into RAM.

Thanks.

#nss-spi-dma

[tecnico23]

Posted on April 24, 2012 at 11:15

Hi,

Do you have found a solution for this problem? I've the same application as you. I want to read data from an external ADC for which the start of a new conversion is selected/deselected by the NSS pin. I would also use the DMA.

A solution could be the TI SPI mode, but the clock phase and polarity configured by the TI SPI mode, isn't equal to what I need.

Regards,

A.Paiva

[tecnico23]

Posted on April 24, 2012 at 13:55

May be it could work using the NSS configured as an PWM output pin, but you should make sure that the PWM will start before the clock and you should make sure that you configure correctly the duty cycle and the frequency. But this is so far the solution that I would like to use, because if there is an delay in the SPI peripheral, the sincronization between the PWM output signal won't failure with the clock signal.

Does someone have any sugestions to this post? I think that this is an inportant topic for the most people who use SPI to communicate with other devices.

Regards,

A. Paiva

[alok472]

Posted on April 24, 2012 at 19:29

Not sure if DMA + SPI is right choice in this case. When running SPI with DMA, the clock are very close and probing SPI CLK will seem that Clock is almost continous. So, NSS not toggling between byte transfer looks logical.

Then what is interesting is to know the ADC conversion time. Can you pls elaborate which ADC is used ?