Disabling the pull-down on PB6 (UCPD1_CC1) via PA9

[BGott.1]

Hello,

we currently have a problem using PB6 of an STM32G474ME as FDCAN-TX: During Reset, it is pulled down to GND, which we attribute to the USB-C functionality. This causes the FDCAN-TX line to send a dominant signal during reset of the STM32.

As per p. 72 of the datasheet for the STM32G474xE (DS12288 Rev 6) the pull-down should be disabled by pulling PA9 low. However, we cannot reproduce this, even though we can disable the pull-down of PB4 via pulling PA10 low.

Is our understanding of the issue correct? Can be pull-down-resistor of PB6 be disabled via other means?

Greetings,

Bernd

[Sarra.S]

Hello @BGott.1​ and welcome to ST Community :smiling_face_with_smiling_eyes:,

In order to disable the pull down on PB6, you only need to set UCPD1_DBDIS bit in the PWR_CR3 register.

Hope that helps!