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turboscrew
Senior III
November 18, 2018
Solved

Device bus cycles (STM32F427)

  • November 18, 2018
  • 7 replies
  • 1324 views

Is there a document that discusses the buses?

I was wondering how much Chrome-Art might affect Flash-Art and CPU, if a picture is stored in flash.

How many bus cycles Chrome-Art takes for a transfer and how does Flash-Art access the flash.

I'm working on something that the bus timing might be important for.

My current guess is that Chrome-Art takes about 10 cycles per transfer and maybe 2 cycles of them are such that Chrome-Art is not using the bus and Flash-Art can use those cycles.

This topic has been closed for replies.
Best answer by Tesla DeLorean

Figure it is designed for code execution and the flash line reads takes 35ns

You can use the cycle timer to time and benchmark things accurately. ​

7 replies

Tesla DeLorean
Tesla DeLoreanBest answer
Guru
November 18, 2018

Figure it is designed for code execution and the flash line reads takes 35ns

You can use the cycle timer to time and benchmark things accurately. ​

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turboscrew
Senior III
November 18, 2018

So no such documents...

Well, thanks.

Tesla DeLorean
Guru
November 19, 2018

>>So no such documents... Well, thanks.

I don't know, I've seen presentations about the ART, and I have a reasonable understanding of the underlying architectures in an SoC context. The CM4 doesn't have an architecturally defined cache, ST bolted something on the side to provide a fast prefetch path based on widening the flash read line width, 128-bit as I recall.

It really isn't geared to one-time, non-temporal use, or access via DMA, etc. In the worst case it is going to cause bus contention, likely blocking for 6 cycles or more, per access.

Where documentation is lacking, or of questionable value, one has to read between the lines, apply knowledge of other ARM implementations, and formulate tests to prove or disprove the viability of different methods.

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turboscrew
Senior III
November 19, 2018

Yes, I have searched ARM pages if something is missing from the STM32-documentations. Sometimes I have found something.

Like the description of bus matrix IP.

waclawek.jan
Super User
November 18, 2018

DMA2D_AMTCR is there to limit the impact of DMA2D to other bus masters.

I'd suggest to benchmark.

JW

waclawek.jan
Super User
November 18, 2018

DMA2D_AMTCR is there to limit the impact of DMA2D to other bus masters.

I'd suggest to benchmark.

JW

turboscrew
Senior III
November 19, 2018

It seems to be the only way...

The chip even has the trace cell, but I don't have any trace-capable POD. :(