DAP access to SRAM

[Ted Carter]

Posted on May 08, 2018 at 22:52

Hi -

Is it possible for a debugger to directly r/w to embedded SRAM via one of the debug APs (access ports) on the

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  That is, I don't want to access SRAM via the M7 since the &sharpcache might be enabled.  I'd like to inspect SRAM contents, not the cache. 

According to the TRM, AP0 is dedicated to the M7, so I assume SRAM access will be through the M7/cache.  AP1 (D3 AHB interconnect) looks right, but I did some experiments that suggesting that access is also through M7.   Could someone clarify?

Regards, Ted.

#stm32h7x3? #stm32h7x3

[Ted Carter]

Posted on May 09, 2018 at 02:14

I think I already found the error in my ways...

Reading/writing to SRAM regions through AP0 will not be via the M7 but the AXI bus matrix.  This access will of course have coherency issues when the M7 cache is enabled.  To have a view into the cache, I would assume one would need to use DCC or equivalent registers.

Regards, Ted.