Custom USART for STM32103VE

[brilloeugene]

Posted on October 16, 2015 at 05:23

Hello.

I have to use asynchronous and synchronous modes. For asynchronous, I'm already using the built-in USART peripheral. My problem is the synchronous one. My clock needs to be 16 ticks per bit and more importantly, I should use the same pins for RX and TX for the two modes.

The only solution that I can think of is to just use the GPIO pins and create the waveform myself. May I know if there is an easier way compared to this?

Thanks.

#usart #stm32

[Tesla DeLorean]

Posted on October 16, 2015 at 05:56

One clock for both, or independent clocks for Tx and Rx? Who generates the clock(s)?

EXTI interrupts sending/receiving bits?

DMA+TIM+GPIO outputting pin sequences from a pattern buffer?

[brilloeugene]

Posted on October 16, 2015 at 07:25

Hello. Same CLK for RX and TX and generated by stm32.

I don't know yet EXTI Interrupts and DMA. I'll read about them.

[brilloeugene]

Posted on October 25, 2015 at 08:27

Hello clive1, I tried GPIO only and Systick timer+GPIO but I can't reach 5 Mhz clock that is around 50% duty cycle. Is this even possible? Thanks.

[Tesla DeLorean]

Posted on October 25, 2015 at 18:21

Well how fast exactly do you expect/need this thing to be?

Perhaps if you're working with odd protocols, and data rates >1Mbps, you might consider doing it with a CPLD or FPGA?

The F1 is a rather old part, where the GPIO is attached to a peripheral bus (APB), rather than a hardware bus (AHB). I suspect it might support signal pattern generation in the 8-9 MHz range. And interrupts up a few 100 KHz.

[brilloeugene]

Posted on October 26, 2015 at 01:46

5 Mhz is the clock I need. When toggling the clock pin alone, it is almost 40-50% duty cycle. But when I also modify the data pin, the clock seems random at 2-5 Mhz.

Unfortunately for me, CPLDA or FPGA is not possible.

[Tesla DeLorean]

Posted on October 26, 2015 at 02:06

Should I try and imagine what you are doing?