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Elwood Downey
Elwood Downey
Associate III
Dec 15, 2016 10:38 PM UTC
Solved

CubeMX shows incorrect I2S in Clock view

Posted on December 15, 2016 at 23:38

Just wanted to mention a small bug in CubeMX 4.18.0. I am using STM32F446ZET. It has two I2S peripherals. When I configure I2S1 in the Pinout tab, the Clock tab shows the clocks wired for I2S2. And vice versa. The chosen pins, Configuration and generated code are all correct, it just seems the Clock view gets them swapped.

    This topic has been closed for replies.
    Imen.DBest answer
    ST Technical Moderator
    Dec 16, 2016 11:37 AM UTC
    Posted on December 16, 2016 at 12:37

    Dear

    Downey.Elwood

    ‌,

    After checking, this is not a bug, as

    clock for

    I2S1 mapped on APB2 and clock for I2S2 mapped on APB1.

    This is mentioned in the RM0390 (page 116):

    '

    I2S1/2 clocks

    To achieve high-quality audio performance and for a better configuration flexibility, the I2S1 clock and I2S2 clock (which are respectively clocks for I2Ss mapped on APB1 and APB2) can be derived from four sources: specific main PLL output, a specific PLLI2S output, from an external clock mapped on the I2S_CKIN pin or from HSI/HSE

    '

    Best Regards

    -Imen-

    In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
    View in thread

    4 replies

    Imen.DBest answer
    ST Technical Moderator
    Dec 16, 2016 11:37 AM UTC
    Posted on December 16, 2016 at 12:37

    Dear

    Downey.Elwood

    ‌,

    After checking, this is not a bug, as

    clock for

    I2S1 mapped on APB2 and clock for I2S2 mapped on APB1.

    This is mentioned in the RM0390 (page 116):

    '

    I2S1/2 clocks

    To achieve high-quality audio performance and for a better configuration flexibility, the I2S1 clock and I2S2 clock (which are respectively clocks for I2Ss mapped on APB1 and APB2) can be derived from four sources: specific main PLL output, a specific PLLI2S output, from an external clock mapped on the I2S_CKIN pin or from HSI/HSE

    '

    Best Regards

    -Imen-

    In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
    waclawek.jan
    waclawek.jan
    Super User
    Dec 16, 2016 1:32 PM UTC
    Posted on December 16, 2016 at 13:32

    So, if I understand it correctly, the I2S1 *signal* is the clock source for SPI/I2S modules on the APB1 bus, which are namely SPI2/I2S2 and SPI3/I2S3.

    And the I2S2 *signal* is the clock source for SPI/I2S modules on the APB1 bus, which is namely SPI1/I2S1.

    This is a very unfortunately chosen signal naming...

    JW

    Imen.D
    ST Technical Moderator
    Dec 16, 2016 5:05 PM UTC
    Posted on December 16, 2016 at 17:05

    Hello,

    Your comments are reported internally for further review. 

    Thanks for sharing your feedback.

    Best Regards

    -Imen-

    In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
    stm32cube-t
    stm32cube-t
    ST Employee
    Dec 16, 2016 4:44 PM UTC
    Posted on December 16, 2016 at 17:44

    Jan,

    You are correct:

    Sorry for the confusion the user interface may introduce but that's not a bug, MX followed the reference manual naming conventions:

    I2S1 *signal* is the clock source for SPI/I2S modules on the APB1 bus [SPI2/I2S2 and SPI3/I2S3].

    I2S2 *signal* is the clock source for SPI/I2S modules on the APB1 bus [SPI1/I2S1].

    Best regards

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