Correct way to clear TIM_SR_UIF after setting TIM_EGR_UG?

[Uwe Bonnes]

Hello,

to update e,g. PSC before starting a timer, an update event has to be generated. This update event will set UIF and to avoid an interrupt from the update event, the UIF flag needs to be cleared. A sequence

      TIM1->EGR = TIM_EGR_UG;

       TIM1->SR = 0;

TIM1->DIER = TIM_DIER_UIE;

will still immediate generate an interrupt. Having some more commands between event generation and flag clearing fixes the situation.

What is the timing relation between generating an update event and resetting the flag?

Is it enough to have some commands between setting UP and resetting UIF.?

Or is it needed to wait for UIF before resetting it?

[Jan Waclawek]

Oh, this is one of those timing issues ST won't deal with, as "libraries" (SPL, Cube) usually hide them inadvertently through being bloated enough. This particular one has been discussed here several times, e.g. https://community.st.com/s/question/0D50X00009XkZKA/interrupt-on-cen-bit-setting-in-tim7 (March 15, 2013 at 15:46)

I guess I should start writing up the "timing-related issues ST never acknowledged".

JW

[Uwe Bonnes]

I added "while (TIM1->SR ==0);" before clearing SR and placed it as late as possible.

[waclawek.jan]

I found the real one

https://community.st.com/s/question/0D50X00009XkaBtSAJ/tim-delay-needed-between-setting-event-through-egr-and-clearing-sr

JW

[Uwe Bonnes]

Doesn't sound waiting for the flag befor resetting it as an better approach than to sprankle NOP() and unrelated accesses around, as your code does?

But a comment form the IP designers would be find anyways!

[waclawek.jan]

As I mentioned there, both NOPs and accesses to other registers of the same peripheral may be problematic. But then, without intimate knowledge of the internals, any method is - there may be surprises ahead...

Making the relatively sane assumption that the propagation of UIF flag from ERG takes a fixed number of timer-internal-clocks, NOPs gave me an estimate of the time needed - 3 AHB cycles - so even in the most pessimistic scenario, 3 accesses to other registers of the same timer - or *any* 3 operations - should be sufficient. It's more useful to fill other registers than to waste time in wait loops.

> But a comment form the IP designers would be find anyways!

That would amount to a miracle, given ST's approach to this forum.

JW