Connecting STM32 100pin to SRAM 1Mx8bit

[pawelc]

Posted on December 20, 2008 at 18:52

Connecting STM32 100pin to SRAM 1Mx8bit

[pawelc]

Posted on May 17, 2011 at 12:56

Thank you !

Some engineer from ST recomended me to use 16 D-register 16374, in this case there is no need to do any extra inversion of FSMC_NADV signal.

[denkov]

Posted on May 17, 2011 at 12:56

Solution is 74XX573 with inverting NADV.

[pawelc]

Posted on May 17, 2011 at 12:56

Hello

I have to connect STMF103VET6 (100pin case) to typical 8bitx1M SRAM, only mux mode is possible in this case, 8 bits of lower adress word and 8 bit data are multiplexed.

In datasheet I can't find any explanation.

So I've got two questions:

1. I think I need use D-latch like 74LVC573, is it a correct idea??

2. FSMC_NADV signal is used to latch the adress?, if yes can I change polarity of this signal? (on figure 25 page 60 manual), think I need active high polarity and falling edge to latch adress.

Does anybody has any experience in this connection, and can help me solve this problem?

Thanks for friendly advices.

Pawel