Confused with USB FIFO Allocation

[dimax]

Posted on February 25, 2013 at 13:01

This is a piece of code from usb_core.c

/* set Rx FIFO size */

USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);

/* EP0 TX*/

nptxfifosize.b.depth = TX0_FIFO_FS_SIZE;

nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;

USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );

It allocatesRX_FIFO_FS_SIZE for RX_FIFO and starts EP0 TX FIFO at

nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;

But according to reference manualDIEPTXF0_HNPTXFSIZ is allocated in 32-bit words. So actuallyRX_FIFO_FS_SIZE*4 were allocated and thus TX0 FIFO should start atRX_FIFO_FS_SIZE*4 address.

Where a bug is? Is it in source code or in reference manual?

[tsuneo]

Posted on February 26, 2013 at 07:43

You are mixing up ''address'' and ''size''.

Address starts from zero, as usual in digital sense.

When the RX memory block of RX_FIFO_FS_SIZE is taken from zero, the next block (for non-periodical TX) starts at RX_FIFO_FS_SIZE.

next start address = 0 + RX_FIFO_FS_SIZE = RX_FIFO_FS_SIZE

The value of RX_FIFO_FS_SIZE should be aware of 4-byte alignment (ie. multiple of 4).

Tsuneo

[dimax]

Posted on February 26, 2013 at 07:49

It is all clear to me.

I was confused about sentence in reference manual ''

is allocated in terms of 32-bit words.''

It means that value is multiplied by 4. I tihnk you are right that it is just 4 bytes aligned and it is a mistake in manual.