Configure SRAM as non-cacheable in MPU

[ranran]

Hello,

In stm32h7 I see in the "System architecture" diagram that SRAM3,SRAM2,SRAM1 are not passing through the cache.

Yet, it seems that when using SRAM3 with DMA I must configure it as non-cacheable, otherwise I get junk in data.

Can anyone please explain why it must be configured as non-cacheable in MPU ?

Thanks

[Piranha]

AN4891 Figure 1. Through what path the CPU accesses the SRAM1-3?

[Tesla DeLorean]

Nonsense, the cache is on the processor, not on the bus, the SRAM1, SRAM2 and SRAM3 are cached.

Look at the MPU_Config() examples, there are literally dozens in the HAL software trees.

[berendi]

Looks like the cache is omitted in RM0399 (H7x5/H7x7), but it's properly drawn in RM0433 (H7x3/H750).

Or maybe the I$ and D$ symbols are supposed to mean instruction and data cache? An incredibly lame pun (cash = cache) that has no place in a technical documentation.