Common-mode voltage on USB on STM32F103

[pgregson1]

Posted on February 13, 2017 at 23:50

Hello,

I hope someone can clarify this. How can the USB common mode range be less than 3 volts if  D  and D- pulled down with 15k, differential resistance is 90 ohms, and pullup is 1.5k to 3.3 volts?  Using simple network theory, the voltage must be

             3.6 x (15k || (15k + 90))  / (1.5k+(15k || (15k+90))) = 3.0 volts 

The STM32F103C6 data sheet specifies the characteristic impedance is 90 ohms, and states in table 44 on page 69 that the USB common-mode voltage range is 0.8 volts minimum to 2.5 volts maximum, measured from the local ground.

How can this be?  What am I missing?

Thanks

Peter

[T J]

Posted on February 14, 2017 at 00:38

The USB input is a differential opamp, and by the data sheet must have a minimum 0.2V differential to ensure correct operation.

in the reference article below;

Defining input common-mode range

When speaking of op amp inputs, input common-mode voltage (VICM) is one of the first terms of which an engineer thinks, but may lead to some initial confusion. VICM describes a particular voltage level and is defined as the average voltage at the inverting and non-inverting input pins.

2.5V is the average of the two states 0v and 5V

in the F103 data sheet;

(VDI) Differential input sensitivity I(USB_DP, USB_DM)       0.2V (minimum swing for correct operation)

(VCM) Differential common mode range                               0.8 - 2.5V ( requested swing for correct operation)

Guaranteed by characterization results, not tested in production.

absolute maximums,

(VIN)  Input voltage on five volt tolerant pin VSS − 0.3 , VDD + 4.0

don't exceed 5V to satisfy the USB differential input.

don't exceed Vdd + 4V ( 7.6V MAX) to satisfy 5V tolerant input.

don't expose a 5V tolerant input to less than -0.3V

 

reference:

http://www.planetanalog.com/document.asp?doc_id=528175

 

other that that you can do anything you like...

ESD protection is necessary if you are using a USB socket whilst your processor is powered on.

[pgregson1]

Posted on February 14, 2017 at 12:52

All true.  However, tbe common mode voltage limit must be adhered to even when there is no traffic on the bus. In that situation, the average voltage is 3 volts (as shown both above and on my calibrated 200 MHz oscillloscope) and that violates the specification.  It appears that neither the host nor the  STM32F103 is driving the bus, which makes sense for a bidirectional bus when there is no traffic, so D+ abd D- float to the voltage calculated above, 3 volts.

So what gives?

Regards,

Peter

[T J]

Posted on February 14, 2017 at 13:20

Digital electronics and a lot more forgiving than analog circuits, as such, we expect to see rail voltages.

This allows the digital signals to pack more information into a time space, whereas analog signals are hard to stabilize and so need settling time and high precision components, then suffer from drift and re-calibration periodically.

USB1.0, USB2.0 USB3.0, RS485, LVDS, DSI are all high speed differential signals in the digital realm and so usually have signals at the opposing rails.

USB , being a single differential pair (a single channel), is by design, half duplex, where there are three states:

either the master is driving the line,

or the the slave is driving the line,

or neither is driving the line.

When the USB line is idle there is no 90ohm drive present, only the passive pull up and pull down resistors.

The input common-mode range is defined as the average voltage of the inverting and non-inverting input pins.

I believe that one leg will be 3V and the other will be 0 volts at idle, that averages to 1.5V

hence the absolute maximum (VCM) is (3+0) / 2  = 1.5V or less at all times.

[pgregson1]

Posted on February 14, 2017 at 14:02

I was missing the fact that the 90-ohm bus termination was disconnected from the bus when the bus was not driven.  However, does that mean that the bus is terminated only from the driving end?  Presumably the receiver doesn't 'know' that ther is about to be an incoming message and so when it is listening, the bus is not terminated at its end.  Is that correct?

Best regards,

Peter

[T J]

Posted on February 14, 2017 at 14:45

Actually, I thought the SOF pulses would be running continuously, that's the Master asking if the slave wants to chat.

(much like a start bit from the master)

If the slave is ready to transmit something, it waits for the SOF and then it will transmit...

also, it is not a 90ohm termination as such, it is a 90ohm drive impedance... and yes only present when it is driven.

I am not an expert, I think it is very difficult to be an expert in any field... there is just tooo much to know.

So please take my advice with a grain of salt..

If someone else has a more in-depth understanding, please chime in...

[pgregson1]

Posted on February 14, 2017 at 14:56

There seems to be idle time between the SOF pulses.  Of course, there must be because the host has to release the bus to give the device a chance to answer the SOF packet.  

With respect to the 90-ohm termination, what you say is obvious to me now.  It is easy to lock on to an incorrect view of the situation when you unknowingly make an assumption.  In my experience, that assumption is almost always wrong.

Thanks for helping me to see the situation for what it is.

Best regards,

Peter